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| 4559 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0188-0104 Rev.1.04 Aug 23, 2007 DESCRIPTION The 4559 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 Series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has one or two reload registers), a 16-bit timer for clock count, interrupts, and oscillation circuit switch function. The various microcomputers in the 4559 Group include variations of type as shown in the table below. FEATURES * Minimum instruction execution time..............................0.5 s (at 6 MHz oscillation frequency, in high-speed through-mode) * Supply voltage .......................................................1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) * Timers Timer 1..............................................................8-bit timer with a reload register and carrier wave output auto-control function Timer 2.....................................................................8-bit timer with two reload registers and carrier wave generation circuit Timer 3........................ 16-bit timer (fixed dividing frequency) Interrupt ..................................................................... 4 sources Key-on wakeup function pins .............................................. 17 I/O port ................................................................................. 22 Output port ............................................................................. 3 LCD control circuit Segment output ..................................................................... 32 Common output ...................................................................... 4 * Voltage drop detection circuit Reset occurrence..................................Typ. 1.7 V (Ta = 25 C) Reset release ........................................Typ. 1.8 V (Ta = 25 C) Skip occurrence ...................................Typ. 2.0 V (Ta = 25 C) * Power-on reset circuit * Watchdog timer * Clock generating circuit Built-in clock (on-chip oscillator) Main clock (ceramic resonator/RC oscillation) Sub-clock (quartz-crystal oscillation) * LED drive directly enabled (port D) APPLICATION Remote control transmitter * * * * * Table 1 Support Product ROM size (x 10 bits) 6144 words 6144 words RAM size (x 4 bits) 288 words 288 words Package PLQP0052JA-A PLQP0052JA-A QzROM QzROM ROM type Part number M34559G6FP (Note 1) M34559G6-XXXFP Note 1: Shipped in blank Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 1 of 146 4559 Group PIN CONFIGURATION Pin configuration (top view) P10/SEG20 P03/SEG19 P02/SEG18 P01/SEG17 P00/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 30 SEG10 29 39 38 37 36 35 34 33 32 31 28 P11/SEG21 P12/SEG22 P13/SEG23 P20/SEG24 P21/SEG25 P22/SEG26 P23/SEG27 P30/SEG28 P31/SEG29 P32/SEG30 P33/SEG31 D0 D1 27 SEG9 SEG8 40 41 42 43 44 45 46 47 48 49 50 51 52 10 11 12 13 1 2 3 4 5 6 7 8 9 26 25 24 23 22 M34559G6FP M34559G6-XXXFP 21 20 19 18 17 16 15 14 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2/VLC1 SEG1/VLC2 SEG0/VLC3 COM3 COM2 COM1 COM0 VDCE XCIN/D6 XCOUT/D7 XOUT D2 D3 D4 XIN OUTLINE PLQP0052JA-A (52P6A-A) Fig 1. Pin configuration (PLQP0052JA-A type) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 2 of 146 VDD C/CNTR CNVss D5/INT RESET Vss 4559 Group Fig 2. 4 4 4 4 2 6 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Port P0 Port P3 Port P1 Port P2 Port D FUNCTIONAL BLOCK DIAGRAM I/O port Internal peripheral functions Timer XIN-XOUT (Ceramic/RC) XCIN-XCOUT (Quartz-crystal) On-chip oscillator Power-on reset circuit Voltage drop detection circuit System clock generating circuit Functional block diagram (PLQP0052JA-A type) Page 3 of 146 Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (16 bits) Memory ROM 6144 words x 10 bits Watchdog timer (16 bits) 4500 Series CPU core ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) RAM 288 words x 4 bits LCD display RAM including 32 words x 4 bits LCD drive control circuit (Max.32 segments x 4 common) Segment output Common output Port C 32 4 1 4559 Group PERFORMANCE OVERVIEW Table 2 Performance overview Parameter Number of basic instructions Minimum instruction execution time Memory sizes I/O port ROM RAM D0-D5 I/O (Input is examined by skip decision.) Output I/O 135 0.5 s (Oscillation frequency 6 MHz: high-speed through mode) 6144 words x 10 bits 288 words x 4 bits (including LCD display RAM 32 words x 4 bits) Six independent I/O ports. The output structure can be switched by software. Port D5 is also used as INT pin. Two independent output ports. Ports D6 and D7 are also used as XCIN and XCOUT, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P00-P03 are also used as SEG16-SEG19, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P10-P13 are also used as SEG20-SEG23, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P20-P23 are also used as SEG24-SEG27, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. Ports P30-P33 are also used as SEG28-SEG31, respectively. 1-bit output; Port C is also used as CNTR pin. 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. 8-bit timer with two reload registers and carrier wave generation function. 16-bit timer, fixed dividing frequency (timer for clock count) 4-bit programmable timer with a reload register (for LCD clock generating) 16-bit timer, fixed dividing frequency (timer for monitor) 1/2, 1/3 bias 2, 3, 4 duty 4 32 2r x 3, 2r x 2, r x 3, r x 2 (r = 100 k, (Ta = 25 C, Typical value)) Typ. 1.7 V (Ta=25 C) Typ. 1.8 V (Ta=25 C) Typ. 2.0 V (Ta=25 C) Built-in 4 sources (one for external, three for timers) 1 level 8 levels CMOS silicon gate 52-pin plastic molded LQFP (PLQP0052JA-A) -20 to 85 C 1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) 0.3 mA (Ta = 25 C, VDD = 3 V, f(XIN) = 4 MHz, f(XCIN) = stop, f(RING) = stop, f(STCK) = f(XIN)/8 5 A (Ta = 25 C, VDD = 3 V, f(XCIN) = 32 kHz) 0.1 A (Ta = 25 C, VDD = 5 V, output transistor is cut-off state) Function D6, D7 P00-P03 P10-P13 I/O P20-P23 I/O P30-P33 I/O C Timer Timer 1 Timer 2 Timer 3 Timer LC Output Watchdog timer LCD control circuit Selective bias value Selective duty value Common output Segment output Internal resistor for power supply Voltage drop detection circuit Reset occurrence Reset release Skip occurrence Power-on reset circuit Interrupt Subroutine nesting Device structure Package Operating temperature range Power source voltage At active mode Power dissipation (Typ. value) At clock operating mode At RAM back-up Source Nesting Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 4 of 146 4559 Group PIN DESCRIPTION Table 3 Pin VDD VSS CNVSS VDCE Pin description Name Power source Power source CNVSS Voltage drop detection circuit enable Main clock input Main clock output Input/Output - - - Input Connected to a plus power supply. Connected to a 0 V power supply. This pin is shared with the VPP pin which is the power source input pin for programming the built-in QzROM. Connect to VSS through a resistor about 5 k. This pin is used to operate/stop the voltage drop detection circuit. When "H" level is input to this pin, the circuit starts operating. When "L" level is input to this pin, the circuit stops operating. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs "L" level. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port D5 is also used as INT pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P00-P03 are also used as SEG16-SEG19, respectively. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P10-P13 are also used as SEG20-SEG23, respectively. Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P2 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P20-P23 are also used as SEG24-SEG27, respectively. Port P3 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P3 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P30-P33 are also used as SEG28-SEG31, respectively. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0- COM2 are used at 1/3 duty and pins COM0-COM3 are used at 1/4 duty. LCD segment output pins. SEG0-SEG2 pins are used as VLC3-VLC1 pins, respectively. SEG16-SEG31 pins are used as Ports P00-P03, Ports P10-P13, Ports P20-P23, and Ports P30-P33, respectively. CNTR pin has the function to input the clock for the timer 1 event counter and to output the PWM signal generated by timer 2. CNTR pin is also used as Port C. INT pin accepts external interrupts. They have the key-on wakeup function which can be switched by software. INT pin is also used as Port D5. These are the LCD power supply pins. If an internal resistor is used, connect the VLC3 pin to the VDD pin. (If brightness adjustment is required, connect via a resistor.) When using an external power supply, apply voltage such that VSS VLC1 VLC2 VLC3 VDD. Pins VLC3 to VLC1 also function as pins SEG0 to SEG2. Function XIN XOUT Input Output XCIN XCOUT RESET Sub clock input Sub clock output Reset I/O Input Output I/O D0-D5 I/O port D (Input is examined by skip decision.) Output port D I/O D6, D7 Output P00-P03 I/O port P0 I/O P10-P13 I/O port P1 I/O P20-P23 I/O port P2 I/O P30-P33 I/O port P3 I/O C Output port C Output Output Output COM0-COM3 Common output SEG0-SEG31 Segment output CNTR INT VLC3-VLC1 Timer I/O Interrupt input LCD power source I/O Input - Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 5 of 146 4559 Group MULTIFUNCTION Table 4 Pin P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 Pin description Multifunction SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Pin SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Multifunction P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 D5 D6 D7 C SEG0 SEG1 SEG2 Pin Multifunction SEG28 SEG29 SEG30 SEG31 INT XCIN XCOUT CNTR VLC3 VLC2 VLC1 Pin SEG28 SEG29 SEG30 SEG31 INT XCIN XCOUT CNTR VLC3 VLC2 VLC1 Multifunction P30 P31 P32 P33 D5 D6 D7 C SEG0 SEG1 SEG2 Note 1. Pins except above have just single function. Note 2. The input/output of D5 can be used even when INT is selected. Be careful when using inputs of both INT and D5 since the input threshold value of INT pin is different from that of port D5. Note 3. "H" output function of port C can be used even when the CNTR (output) is used. PORT FUNCTION Table 5 Port Port D Port function Pin D0-D4, D5/INT D6/XCIN, D7/XCOUT Input Output I/O (6) Output (2) I/O (4) Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS CMOS 4 bits OP0A IAP0 I/O unit 1 bit Control instructions SD, RD SZD, CLD Control registers FR1, FR2, I1, K2 RG PU0, K0, FR0, C1 Remark Programmable output structure selection function - Programmable pull-up, keyon wakeup and output structure selection function Programmable pull-up, keyon wakeup and output structure selection function Programmable pull-up, keyon wakeup and output structure selection function Programmable pull-up, keyon wakeup and output structure selection function - Port P0 P00/SEG16, P01/SEG17, P02/SEG18, P03/SEG19 P10/SEG20, P11/SEG21, P12/SEG22, P13/SEG23 P20/SEG24, P21/SEG25, P22/SEG26, P23/SEG27, P30/SEG28, P31/SEG29, P32/SEG30, P33/SEG31 C/CNTR Port P1 I/O (4) 4 bits OP1A IAP1 PU1, K0, FR0, C2 Port P2 I/O (4) 4 bits OP2A IAP2 PU2, K1, FR3, L3 Port P3 I/O (4) 4 bits OP3A IAP3 PU3, K2, K3, FR2, C3 Port C Output (1) 1 bit RCP SCP W1, W2, W4 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 6 of 146 4559 Group DEFINITION OF CLOCK AND CYCLE * Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * Clock (f(XIN)) by the external ceramic resonator * Clock (f(XIN)) by the external RC oscillation * Clock (f(XIN)) by the external input * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator * Clock (f(XCIN)) by the external quartz-crystal oscillation * System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. * Machine cycle The machine cycle is the standard cycle required to execute the instruction. * Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. Table 6 MR3 1 1 0 0 1 1 0 0 1 1 0 0 Table Selection of system clock Register MR MR2 1 0 1 0 1 0 1 0 1 0 1 0 MR1 0 0 0 0 0 0 0 0 1 1 1 1 MR0 0 0 0 0 1 1 1 1 0 0 0 0 System clock f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode Low-speed frequency divided by 8 mode Low-speed frequency divided by 4 mode Low-speed frequency divided by 2 mode Low-speed through mode Note 1. The f(RING)/8 is selected after system is released from reset Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 7 of 146 4559 Group CONNECTIONS OF UNUSED PINS Table 7 Pin XIN XOUT XCIN/D6 XCOUT/D7 D0-D4 D5/INT P00/SEG16- P03/SEG19 Open. Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Port function Connection Connect to VSS. RC oscillator is not selected - - - - N-channel open-drain is selected for the output structure. INT pin input is disabled. N-channel open-drain is selected for the output structure. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. CNTR input is not selected for timer 1 count source. - SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected. - Usage condition P10/SEG20- P13/SEG23 Open. Connect to VSS. P20/SEG24- P23/SEG27 Open. Connect to VSS. P30/SEG28- P33/SEG31 Open. Connect to VSS. C/CNTR COM0-COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3-SEG15 Open. Open. Open. Open. Open. Open. (Note when connecting to VSS or VDD) Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 8 of 146 4559 Group PORT BLOCK DIAGRAM Skip decision Register Y Decoder SZD instruction (Note 3) CLD instruction S SD instruction RD instruction RQ FR1i (Note 1) D0-D3 (Note 2) (Note 1) Skip decision Register Y Decoder SZD instruction FR20 CLD instruction S SD instruction RD instruction RQ (Note 1) (Note 1) D4(Note 2) Skip decision Register Y Decoder SZD instruction FR21 CLD instruction SD instruction RD instruction S RQ (Note 1) D5/INT(Note 2) (Note 1) External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input External 0 interrupt circuit (Note 4) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. i represents bits 0 to 3. 4. As for details, refer to the external interrupt structure. Fig 3. Port block diagram (1) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 9 of 146 4559 Group Register Y Decoder CLD instruction (Note 1) S RQ RG2 1 0 XCIN/D6 (Note 2) (Note 1) SD instruction RD instruction Sub-clock input Quartz-crystal oscillation circuit RG2 (Note 1) RG2 1 0 XCOUT/D7 (Note 2) (Note 1) Register Y Decoder CLD instruction SD instruction RD instruction S RQ Clock input for timer 1 event count Timer 1 underflow signal W41 T R W12 PWMOD SCP instruction RCP instruction SQ R W10 W11 (Note 1) C/CNTR (Note 2) (Note 1) Q D Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. Fig 4. Port block diagram (2) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 10 of 146 4559 Group LCD power supply 0 LCD control signal 1 C1j (Note 3) (Note 1) P00/SEG16, P01/SEG17 (Note 1) (Note 2) LCD power supply (Note 3) C1j K00 Key-on wakeup input Edge detection circuit (Note 3) Register A Aj IAP0 instruction Pull-up transistor FR00 Aj D Q PU0j (Note 3) OP0A T instruction LCD power supply LCD control signal 0 1 C1K (Note 4) (Note 1) P02/SEG18, P03/SEG19 (Note 1) (Note 2) LCD power supply (Note 4) C1K K01 Key-on wakeup input Edge detection circuit IAP0 (Note 4) instruction Register A Ak Pull-up transistor FR01 Ak OP0A instruction D T Q PU0k (Note 4) Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. Fig 5. Port block diagram (3) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 11 of 146 4559 Group LCD power supply 0 LCD control signal 1 C2j (Note 3) (Note 3) C2j K02 Key-on wakeup input Edge detection circuit (Note 3) Register A Aj IAP1 instruction LCD power supply (Note 1) P10/SEG20, P11/SEG21 (Note 1)(Note 2) Pull-up transistor FR02 Aj OP1A instruction D T Q PU1j (Note 3) LCD power supply LCD control signal 0 1 C2k (Note 4) (Note 4) C2k K03 Key-on wakeup input Edge detection circuit (Note 4) Register A Ak IAP1 instruction LCD power supply (Note 1) P12/SEG22, P13/SEG23 (Note 1)(Note 2) Pull-up transistor FR03 Ak D Q PU1k (Note 4) OP1A T instruction Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. Fig 6. Port block diagram (4) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 12 of 146 4559 Group LCD power supply 0 LCD control signal 1 L3j (Note 3) (Note 3) L3j K1j Key-on wakeup input Edge detection circuit IAP2 (Note 3) instruction Register A Aj LCD power supply (Note 1) P20/SEG24, P21/SEG25 (Note 2) (Note 1) Pull-up transistor FR3j Aj D Q PU2j (Note 3) OP2A T instruction LCD power supply LCD control signal 0 1 L3k (Note 4) (Note 4) L3k K1k Key-on wakeup input Edge detection circuit IAP2 (Note 4) instruction Register A Ak LCD power supply (Note 1) P22/SEG26, P23/SEG27 (Note 1) (Note 2) Pull-up transistor FR3k Ak D Q PU2k (Note 4) OP2A T instruction Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. Fig 7. Port block diagram (5) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 13 of 146 4559 Group LCD power supply 0 LCD control signal 1 C3j (Note 3) (Note 5) K31 0 Key-on wakeup input 1 Edge detection circuit Edge detection circuit (Note 5) K30 0 1 (Note 3) Register A Aj (Note 5) K22 (Note 3) C3j LCD power supply (Note 1) P30/SEG28, P31/SEG29 (Note 2) (Note 1) IAP3 instruction Pull-up transistor FR22 Aj OP3A instruction D T Q PU3j (Note 3) LCD power supply 0 LCD control signal 1 C3k (Note 4) (Note 1) P32/SEG30, P33/SEG31 (Note 1)(Note 2) LCD power supply (Note 6) K33 Key-on wakeup input 0 1 Edge detection circuit Edge detection circuit (Note 6) K32 0 1 (Note 4) Register A Ak (Note 6) K23 (Note 4) C3k IAP3 instruction Pull-up transistor FR23 Ak D Q PU3k (Note 4) OP3A T instruction Notes 1. 2. 3. 4. 5. This symbol represents a parasitic diode on the port. Applied potential to these ports must be VDD or less. j represents bits 0, 1. k represents bits 2, 3. For setting key-on wakeup of ports P30 and P31 to be invalid (K22 = "0") set registers K30 and K31 to "0." 6. For setting key-on wakeup of ports P32 and P33 to be invalid (K23 = "0") set registers K32 and K33 to "0." Fig 8. Port block diagram (6) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 14 of 146 4559 Group LCD power supply LCD control signal (Note 1) SEG3-SEG15 (Note 2) (Note 1) LCD control signal LCD power supply LCD power supply LCD control signal (Note 1) COM0-COM3 (Note 2) (Note 1) LCD control signal LCD power supply LCD power supply LCD control signal LCD control signal Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. Fig 9. Port block diagram (7) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 15 of 146 4559 Group LCD power supply 0 LCD control signal 1 L23 (Note 1) SEG0/VLC3 (Note 2) L23 0 LCD power supply (VLC3) 1 0 L13 LCD power supply 0 1 L22 1 L23 LCD power supply (Note 1) LCD control signal 0 1 L20 L22 0 LCD power supply (Note 1) SEG1/VLC2 (Note 2) (Note 1) LCD power supply (VLC2) 1 1 L22 LCD power supply 0 1 0 1 L11 0 LCD control L13 signal L21 (Note 1) SEG2/VLC1 (Note 2) L21 0 LCD power supply (VLC1) 1 L20 (Note 1) LCD power supply 0 1 L21 1 0 L13 Reset signal L12 EPOF instruction + POF instruction Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. L20 Fig 10. Port block diagram (8) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 16 of 146 4559 Group (Note 1) D5/INT (Note 1) I12 Falling 0 1 Rising I13 One-sided edge detection circuit I11 0 EXF0 1 External 0 interrupt or Both edges detection circuit SNZI0 instruction Skip decision (Note 2) Level detection circuit K20 Edge detection circuit (Note 3) Timer 1 count start synchronization circuit input K21 0 Key-on wakeup input 1 Notes 1: This symbol represents a parasitic diode on the port. 2: When I12 is 0, "L" level is detected. When I12 is 1, "H" level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected. Fig 11. External interrupt circuit structure Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 17 of 146 4559 Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 12). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 13). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 14). Register E is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value. (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 15). Also, when the TABP p instruction is executed at UPTF flag = "1", the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is "0". When the TABP p instruction is executed at UPTF flag = "0", the contents of register D remains unchanged. The UPTF flag is set to "1" with the SUPT instruction and cleared to "0" with the RUPT instruction. The initial value of UPTF flag is "0". Register D is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value. Fig 12. AMC instruction execution example CY A3 A2 A1 A0 A0 CY A3 A2 A1 Fig 13. RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig 14. Registers A, B and register E ROM Specifying address 8 4 0 TABP p instruction p6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1 DR0 A3 A2 A1 A0 Low-order 2 bits Register A (4) Middle-order 2 bits High-order 2 bits Register B (4) Register D (3) Field value p The contents of register D The contents of register A Flag UPTF = 1; High-order 2 bits of reference data is transferred to the low-order 2 bits of register D. "0" is stored to the high-order 1 bit of register D. Flag UPTF = 0; Data is not transferred to register D. Fig 15. TABP p instruction execution example Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 18 of 146 4559 Group (5) Stack registers (SKs) and stack pointer (SP) Stack registers are 14-bit registers. Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 16 shows the stack registers (SKs) structure. Figure 17 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points "7" at reset or returning from power down mode. It points "0" b y executing the first B M instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig 16. Stack registers (SKs) structure (SP) 0 (SK0) 000116 (PC) SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1: NOP RT ... (PC) (SK0) (SP) 7 Note :Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig 17. Example of operation at subroutine call Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 19 of 146 4559 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 18). Make sure that the PCH does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 19). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 20). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these registers. Program counter (PC) p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig 18. Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig 19. Data pointer (DP) structure Specifying bit position Set D3 0 0 0 1 Register Y (4) D2 D1 1 D0 Port D output latch Fig 20. SD instruction execution example Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 20 of 146 4559 Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 21 shows the ROM map of M34559G6. Table 8 ROM size and pages ROM (PROM) size (x 10 bits) 6144 words Pages 48 (0 to 47) 98 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 1 0 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 Part number M34559G6 A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 22). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction. ROM Code Protect Address When selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp., reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, whether the ROM code protect is used or not can be selected as ROM option setup ("MASK option" written in the mask file converter) when ordering. 17FF16 Page 47 Fig 21. ROM map of M34559G6 9 008016 008216 008416 008616 008816 008A16 008C16 8 7 6 5 4 3 2 1 0 External 0 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address 00FF16 Fig 22. Page 1 (addresses 008016 to 00FF16) structure Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 21 of 146 4559 Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from power down mode). RAM includes the area for LCD. When writing "1" to a bit corresponding to displayed segment, the segment is turned on. Table 9 shows the RAM size. Figure 23 shows the RAM map. * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in power down mode. After system is returned from the power down mode, set these registers. Table 9 RAM size and pages RAM size 288 words x 4 bits (1152 bits) Part number M34559G6 RAM 288 words x 4 bits (1152 bits) Register Z Register X 0 0 1 2 3 4 5 Register Y 1 2 3 0 ... 12 13 14 15 1 0 1 2 3 6 7 8 9 10 11 12 13 14 15 0 1 8 16 24 9 17 25 2 10 18 26 3 11 19 27 4 12 20 28 5 13 21 29 6 14 22 30 7 15 23 31 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers. Fig 23. RAM map Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 22 of 146 4559 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 10 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 11 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 12 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag except the voltage drop detection circuit interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * a skip instruction is executed. The voltage drop detection circuit interrupt request flag cannot be cleared to "0" at the state that the activated condition is satisfied. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 10. Table 10 Interrupt sources Priority level 1 2 3 4 Interrupt source Activated Interrupt name condition External 0 Level change of interrupt INT0 pin Timer 1 interrupt Timer 1 underflow Timer 2 interrupt Timer 2 underflow Timer 3 interrupt Timer 3 underflow Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Table 11 Interrupt request flag, interrupt enable bit and skip instruction Interrupt request flag External 0 interrupt EXF0 Timer 1 interrupt T1F Timer 2 interrupt T2F Timer 3 interrupt T3F Interrupt name Skip instruction SNZ0 SNZT1 SNZT2 SNZT3 Interrupt enable bit V10 V12 V13 V20 Table 12 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 23 of 146 4559 Group (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 25). * Program counter (PC) An interrupt address is set in program counter. The address to b e e x e c u t e d w h e n r e t u r n i ng t o t h e m a i n r o u t i n e i s automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0". * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 24) * Program counter (PC) Each interrupt address * Stack register (SK) The address of main routine to be executed when returning * Interrupt enable flag (INTE) 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) 0 * Data pointer, carry flag, registers A and B, skip flag Stored in the interrupt stack register (SDP) automatically Fig 25. Internal state when interrupt occurs Activated condition INT pin interrupt waveform input Request flag (state retained) Enable bit Enable flag Address 0 in page 1 EXF0 V10 Timer 1 underflow T1F V12 Address 4 in page 1 Main routine Interrupt service routine Interrupt occurs Timer 2 underflow T2F V13 Address 6 in page 1 Timer 3 underflow T3F V20 INTE Address 8 in page 1 Fig 26. Interrupt system diagram EI RTI Interrupt is enabled : Interrupt enabled state : Interrupt disabled state Fig 24. Program example of interrupt processing Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 24 of 146 4559 Group (6) Interrupt control registers * Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 13 Interrupt control registers Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 Not used 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W TAV1/TV1A * Interrupt control register V2 The timer 3 interrupt enable bit are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) V10 External 0 interrupt enable bit Interrupt control register V2 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 at reset : 00002 at power down : 00002 R/W TAV2/TV2A This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) 1 Interrupt enabled (SNZT3 instruction is invalid) Note 1."R" represents read enabled, and "W" represents write enabled. (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10, V12, V13, V30), and interrupt request flag are set to "1." The interrupt occurs two or three cycles after the cycle where all the above three conditions are satisfied. The interrupt occurs after three machine cycles if instructions other than one-cycle instruction are executed when the conditions are satisfied (Refer to Figure 27). Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 25 of 146 4559 Group Rev.1.04 Aug 23, 2007 REJ03B0188-0104 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared The program starts from the interrupt address. 2 to 3 machine cycles (Notes 1, 2) Fig 27. Interrupt sequence When an interrupt request flag is set after its interrupt is enabled 1 machine cycle Page 26 of 146 System clock (STCK) T1 T2 Interrupt enable flag (INTE) EI instruction execution cycle INT External 0 interrupt EXF0 Timer 1 Timer 2 Timer 3 interrupt T1F T2F T3F Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. 4559 Group EXTERNAL INTERRUPTS The 4559 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Table 14 External interrupt activated conditions Name External 0 interrupt Input pin D5/INT Activated condition When the next waveform is input to D5/INT pin * Falling waveform ("H" "L") * Rising waveform ("L" "H") * Both rising and falling waveforms Valid waveform selection bit I11 I12 (Note 1) D5/INT (Note 1) I12 Falling 0 1 Rising I13 One-sided edge detection circuit I11 0 EXF0 1 Timer 1 count start synchronization circuit input (Note 2) K21 0 1 External 0 interrupt or Both edges detection circuit SNZI0 instruction Skip Level detection circuit K20 Edge detection circuit (Note 3) Key-on wakeup input Note 1: This symbol represents a parasitic diode on the port. 2: When I12= 0(X=0 or 1) is 0, "L" level is detected. When I12 is 1, "H" level is detected. 3: When I12 is 0, falling edge is detected. When I12 is 1, rising edge is detected. Fig 28. External interrupt circuit structure Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 27 of 146 4559 Group (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 27). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D5/INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. (1) Set the bit 3 of register I1 to "1" for the INT pin to be in the input enabled state. (2) Select the valid waveform with the bits 1 and 2 of register I1. (3) Clear the EXF0 flag to "0" with the SNZ0 instruction. (4) Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. (5) Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs. Table 15 External interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected at power down : state retained R/W TAI1/TI1A (2) External interrupt control registers (1) Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 2) I11 I10 INT pin edge detection circuit control bit INT pin timer 1 count start synchronous circuit selection bit Note 1."R" represents read enabled, and "W" represents write enabled. Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 28 of 146 4559 Group (3) Notes on interrupts (1) Bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to (1) in Figure 29.) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to (2) in Figure 29.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 29.). (3) Bit 2 of register I1 When the interrupt valid waveform of the INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to (1) in Figure 31.) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to (2) in Figure 31.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 31.). * * * LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP * * * ; (xxx02) ; The SNZ0 instruction is valid ...... (1) ; (1xxx2) ; Control of INT pin input is changed ...................................................... (2) ; The SNZ0 instruction is executed (EXF0 flag cleared) ...................................................... (3) * * * LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP * * * ; (xxx02) ; The SNZ0 instruction is valid ......(1) ; (x1xx2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ0 instruction is executed (EXF0 flag cleared) .......................................................(3) x: these bits are not used here. x: these bits are not used here. Fig 29. External 0 interrupt program example-1 Fig 31. External 0 interrupt program example-3 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the power down mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the INT pin input is disabled (register I13 = "0"), set the key-on wakeup of INT pin to be invalid (register K20 = "0") before system enters to power down mode. (refer to (1) in Figure 30.). * * * LA 0 TK2A DI EPOF POF2 * * * ; (xxx02) ; INT0 key-on wakeup disabled .....(1) ; RAM back-up x: these bits are not used here. Fig 30. External 0 interrupt program example-2 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 29 of 146 4559 Group TIMERS The 4559 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function). * Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse. FF16 n : Counter initial value Count starts n The contents of counter Reload Reload 1st underflow 2nd underflow 0016 n+1 count Timer interrupt "1" "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count Time Fig 32. Auto-reload function Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 30 of 146 4559 Group The 4559 Group timer consists of the following circuits. * Prescaler : 8-bit programmable timer * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 16-bit fixed frequency timer * Timer LC : 4-bit programmable timer * Watchdog timer: 16-bit fixed frequency timer (Timers 1, 2 and 3 have the interrupt function, respectively) Table 16 Function related timers Circuit Prescaler Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT input) (carrier wave output autocontrol function) 8-bit programmable binary down counter (with carrier wave generation function) 16-bit fixed dividing frequency Count source * Instruction clock (INSTCK) Frequency dividing ratio 1 to 256 Use of output signal * Timer 1 count source * Timer 2 count source * Timer 3 count source * CNTR output control * Timer 1 interrupt Control register PA Prescaler, timer 1, timer 2, timer 3 and timer LC can be controlled with the timer control registers PA and W1 to W4. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Timer 1 * * * * PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow (T3UDF) CNTR input 1 to 256 W1 W4 Timer 2 * XIN input * Prescaler output divided by 2 (ORCLK/2) * XIN input * Prescaler output (ORCLK) 1 to 256 * Timer 1 count source * CNTR output * Timer 2 interrupt * Timer 1 count source * Timer LC count source * Timer 3 interrupt * LCD clock * System reset (counting twice) * Decision of flag WDF1 W2 W4 Timer 3 8192 16384 32768 65536 1 to 16 65536 W3 Timer LC 4-bit programmable binary down counter * Bit 4 of timer 3 (T34) * System clock (STCK) * Instruction clock (INSTCK) W4 - Watchdog 16-bit fixed dividing timer frequency Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 31 of 146 4559 Group Division circuit MR1, MR0 On-chip oscillator Ceramic resonance XIN XCIN RC oscillation Quartz-crystal oscillation Multiplexer (CRCK) 00 01 10 Divided by 8 Divided by 4 Divided by 2 MR3, MR2 11 10 01 00 System clock (STCK) Internal clock generating circuit (divided by 3) Instruction clock (INSTCK) PA0 Prescaler (8) ORCLK Reload register RPS (8) (TPSAB) (TABPS) (TPSAB) (TPSAB) (TABPS) Register B I12 0 D5/INT I13 I10 W13 T1UDF W11, W10 00 01 10 11 W12 (TAB1) Reload register R1 (8) (T1AB) (T1AB) (TR1AB) (T1AB) Register B Register A Timer 1 (8) 1 Register A One-sided edge detection circuit Both edges detection circuit I11 0 S 1 R Q I10 1 0 T1F Timer 1 interrupt Timer 1 underflow signal (T1UDF) PWMOUT ORCLK T3UDF C/CNTR W40 0 1 (TAB1) PWMOUT Port C output D W11 W10 QRT W12 Register B Register A T1UDF W41 (T2HAB) Reload register R2H (8) XIN ORCLK 1/2 W20 0 Timer 2 (8) 1 W21 (TAB2) (T2R2L) Reload register R2L (8) (T2AB) (T2AB) (T2AB) (TAB2) Reload control circuit "H" interval expansion W22 1 0 Q R T PWMOD W23 T2F Timer 2 interrupt Register B Register A Data is set automatically from each reload register when timer underflows (auto-reload function). Fig 33. Timers structure (1) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 32 of 146 4559 Group XCIN ORCLK W33 0 1 W32 Timer 3 (16) 1 - - 4 - - - - - 13 14 15 16 W31, W30 11 10 01 00 T3F Timer 3 interrupt Timer 3 underflow signal (T3UDF) W42 0 Timer LC (4) STCK 1 W43 Reload register RLC (4) 1/2 LCD clock (TLCA) (TLCA) Register A INSTCK Watchdog timer (16) 1 - - - - - - - - - - - - - 16 (Note 1) S WRST instruction Reset signal (Note 3) DWDT instruction + WRST instruction Q WDF1 R S Q D Q Watchdog reset signal reset signal WEF R (Note 2) T R Data is set automatically from each reload register when timer underflows (auto-reload function). Note 1: Flag WDF1 is cleared to "0" and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = "1". The WRST instruction is equivalent to the NOP instruction while flag WDF1 = "0". 2: Flag WEF is cleared to "0" and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 3: The WEF flag is set to "1" at system reset or RAM back-up mode. Fig 34. Timers structure (2) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 33 of 146 4559 Group Table 17 Timer control registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state retained) Operating R/W TAW1/TW1A at power down : 02 W TPAA Timer control register W1 W13 Timer 1 count auto-stop circuit selection bit (Note 2) 0 1 0 1 0 Timer 1 count source selection bits (Note 3) 0 W10 1 1 at reset : 00002 at power down : state retained Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input R/W TAW2/TW2A 0 1 0 1 W12 Timer 1 control bit W11 W10 W11 Timer control register W2 W23 CNTR pin function control bit W22 PWM signal "H" interval expansion function control bit 0 1 0 1 0 1 0 1 at reset : 00002 CNTR pin output invalid CNTR pin output valid at power down : 00002 PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 R/W TAW3/TW3A W21 Timer 2 control bit W20 Timer 2 count source selection bit Timer control register W3 W33 Timer 3 count source selection bit W32 Timer 3 control bit 0 1 0 1 0 Timer 3 count value selection bits W30 0 1 1 at reset : 00002 XCIN input Prescaler output (ORCLK) Stop (initial state) Operating at power down : state retained W31 W30 W31 0 1 0 1 Underflow every 8192 count Count value Underflow every 16384 count Underflow every 32768 count Underflow every 65536 count R/W TAW4/TW4A Timer control register W4 W43 Timer LC control bit W42 Timer LC count source selection bit CNTR pin output auto-control circuit W41 selection bit W40 CNTR pin input count edge selection bit 0 1 0 1 0 1 0 1 at reset : 00002 Stop (state retained) Operating Bit 4 (T34) of timer 3 System clock (STCK) at power down : state retained CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 ="1"). Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 34 of 146 4559 Group (1) Timer control registers * Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. * Timer control register W1 Register W1 controls the count operation and count source of timer 1, and timer 1 count auto-stop circuit. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the count operation and count source of timer 2, CNTR pin output, and extension function of PWM signal "H" interval. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the input count edge of CNTR pin, CNTR1 pin output auto-control circuit. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. (2) Prescaler Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register PA to "1." When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler can be selected the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes "0"), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2 and 3 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with a timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register R1 with the T1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; (1) set data in timer 1 (2) set count source by bit 0 and 1 of register W1, and (3) set the bit 2 of register W1 to "1." When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to "1". Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to "1." (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with two timer 2 reload register (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; (1) set data in timer 2 (2) set count source by bit 0 of register W2, and (3) set the bit 1 of register W2 to "1." When a value set in reload register R2L is n and R2H is m, timer 2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2L, and count continues (autoreload function). When bit 3 of register W2 is set to "1", timer 2 reloads data from reload register R2L and R2H alternately each underflow. Timer 2 generates the PWM signal (PWMOUT) of the "L" interval set as reload register R2L, and the "H" interval set as reload registerR2H. The PWM signal (PWMOUT) is output from CNTR pin. When bit 2 of register W2 is set to "1" at this time, the interval (PWM signal "H" interval) set to reload register R2H for the counter of timer 2 is extended for a half period of count source. In this case, when a value set in reload register R2H is m, timer 2 divides the count source signal by n + 1.5 (m = 1 to 255). When this function is used, set "1" or more to reload register R2H. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 35 of 146 4559 Group When bit 1 of register W4 is set to "1", the PWM signal output to CNTR pin is switched to valid/invalid each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to "0"), this function is canceled. Even when bit 1 of a register W2 is cleared to "0" in the "H" interval of PWM signal, timer 2 does not stop until it next timer 2 underflow. When clearing bit 1 of register W2 to "0" to stop timer 2, avoid a timing when timer 2 underflows. (5) Timer 3 (interrupt function) Timer 3 is a 16-bit binary down counter. Timer 3 starts counting after the following process; (1) set count value by bits 0 and 1 of register W3, (2) set count source by bit 3 of register W3, and (3) set the bit 2 of register W3 to "1." Once count is started, when timer 3 underflows (the set count value is counted), the timer 3 interrupt request flag (T3F) is set to "1," and count continues. Bit 4 of timer 3 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W3 is cleared to "0", timer 3 is initialized to "FFFF16" and count is stopped. Timer 3 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 3 underflow occurs at clock operating mode, system returns from the power down state. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to "1" till executing the POF instruction. (6) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; (1) set data in timer LC, (2) select the count source with the bit 2 of register W4, and (3) set the bit 3 of register W4 to "1." When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes "0"), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock. (7) Timer input/output pin (C/CNTR pin) CNTR pin is used to input the timer 1 count source and output the PWM signal generated by timer 2. The selection of CNTR output signal can be controlled by bit 3 of register W2. When the PWM signal is output from C/CNTR pin, set "0" to the output latch of port C. When the CNTR input is selected for timer 1 count source, timer 1 counts the waveform of CNTR input selected by bit 0 of register W4. Also, when the CNTR input is selected, the output of port C is invalid (high-impedance state). (8) Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to "1" and the control by INT pin input can be performed. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to timer by inputting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to "0" or system reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (10)Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop circuit is valid by setting the bit 3 of register W1 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 36 of 146 4559 Group (11) Precautions * Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. * Timer count source Stop timer 1, 2, 3 or LC counting to change its count source. * Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. * Writing to the timer Stop timer 1, 2 or LC counting and then execute the T1AB, T2AB, T2R2L or TLCA instruction to write data to timer. * Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R2H while the timer 2 is operating, execute the T2HAB instruction except a timing of the timer 3 underflow. * PWM signal If the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When "H" interval expansion function of the PWM signal is used, set "1" or more to reload register R2H. Set the port C output latch to "0" to output the PWM signal from C/CNTR pin. * Timer 3 Stop timer 3 counting to change its count source. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to "1" till executing the POF instruction. * Prescaler and timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 35 after prescaler and timer operations start (1) in Figure 35. Time to first underflow (3) in Figure 35 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 35 by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 1, timer 1 operates synchronizing with the falling edge of CNTR input. (2) Count source Count source (When falling edge of CNTR input is selected) Timer 1 value 3 2 1 0 3 2 1 0 3 2 Timer 1 underflow signal (3) (1) Timer start (4) Fig 35. Timer count start timing and count time when operation starts * Timer 2 and Timer LC count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source operations after count starts. (2) Count source Timer value 3 2 1 0 3 2 1 0 3 Timer underflow signal (3) (1) Timer start (4) Fig 36. Timer count start timing and count time when operation starts (Timer 2 and Timer LC) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 37 of 146 4559 Group - CNTR pin output invalid (W23=0) Timer 2 count source Timer 2 count value (Reload register) 0316 (R2L) (R2L) Timer 2 underflow signal (R2L) (R2L) (R2L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 PWM signal PWM1 signal "L" fixed Timer 2 start - CNTR pin output valid (W23=1), PWM signal "H" interval expansion function invalid (W22=0) Timer 2 count source Timer 2 count value (Reload register) 0316 (R2L) (R2H) Timer 2 underflow signal 4 clock Timer 2 start 3 clock 4 clock 3 clock 4 clock (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 PWM signal PWM period 7 clock PWM period 7 clock - CNTR pin output valid (W23=1), PWM signal "H" interval expansion function valid (W22=1) (Note) Timer 2 count source Timer 2 count value (Reload register) 0316 (R2L) (R2H) Timer 2 underflow signal 4 clock Timer 2 start 3.5 clock 4 clock 3.5 clock 4 clock (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 PWM signal PWM period 7.5 clock PWM period 7.5 clock * : "0316" is set to reload register R3L and "0216" is set to reload register R3H. Note: When the PWM signal "H" interval expansion function is valid, set "1" or more to reload register R2H. Fig 37. Timer 2 operation example Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 38 of 146 4559 Group * CNTR output auto-control circuit operation example 1 (W23 = "1", W41 = "1") PWM signal Timer 1 underflow signal Timer 1 start CNTR output CNTR output start * When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR output is repeated every timer 1 underflows. * CNTR output auto-control circuit operation example 2 (W23 = "1") PWM signal Timer 1 underflow signal Register W41 Timer 1 start (1) (2) Timer 1 stop (3) CNTR output CNTR output start CNTR output stop (1) When the CNTR output auto-control function is not selected while the CNTR output is invalid, CNTR output invalid state is retained. (2) When the CNTR output auto-control function is not selected while the CNTR output is valid, CNTR output valid state is retained. (3) When the timer 1 is stopped, the CNTR output auto-control function becomes invalid. Fig 38. CNTR output auto-control function by timer 1 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 39 of 146 4559 Group Timer 2 count start timing (R2L = "0216", R2H = "0216", W23 = "1") Machine cycle Timer 2 count source (XIN input) Register W21 Timer 2 count value (reload register) Timer 2 underflow signal PWM signal Timer 2 count start timing 0216 (R2L) 0116 0016 0216 (R2H) 0116 0016 0216 (R2L) Mi Mi + 1 TW2A instruction execution (W211) Mi + 2 Mi + 3 Timer 2 count stop timing (R2L = "0216", R2H = "0216", W23 = "1") Machine cycle Timer 2 count source (XIN input) Register W21 Timer 2 count value (reload register) Timer 2 underflow signal PWM signal (Note 1) Timer 2 count stop timing 0216 (R2H) 0116 0016 0216 (R2L) 0116 0016 (R2H) 0216 Mi Mi + 1 Mi + 2 TW2A instruction execution (W210) Mi + 3 Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR pin output is valid (W23="1"), a hazard may occur in the PWM signal waveform. 2: When timer count is stopped during "H" interval of the PWM signal, timer is stopped after the end of the "H" output interval. Fig 39. Timer count start/stop timing Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 40 of 146 4559 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "000016," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. FFFF16 Value of 16-bit timer (WDT) 000016 (2) WDF1 flag (2) When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. 65534 count (Note) WDF2 flag RESET pin output (4) (1) Reset released (3) WRST instruction (5) System reset executed (skip occurrence) (1) After system is released from reset (= after program is started), timer WDT starts count down. (2) When timer WDT underflow occurs, WDF1 flag is set to "1." (3) When the WRST instruction is executed while the WDF1 flag is "1", WDF1 flag is cleared to "0," the next instruction is skipped. (4) When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. (5) The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. Fig 40. Watchdog timer function Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 41 of 146 4559 Group When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 41). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down mode. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction (refer to Figure 42). * * * WRST * * * DI DWDT WRST * * * ; WDF1 flag cleared ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig 41. Program example to start/stop watchdog timer * * * WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF2 ; RAM back-up mode Oscillation stop * * * Fig 42. Program example when using the watchdog timer Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 42 of 146 4559 Group LCD FUNCTION The 4559 Group has an LCD (Liquid Crystal Display) controller/ driver. When data are set in LCD RAM and timer LC, LCD control registers (L1, L2, L3, C1, C2, C3), and timer control registers (W3, W4), the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 32 segment signal output pins can be used to drive the LCD. By using these pins, up to 128 pixels (when internal power, 1/4 duty and 1/3 bias are selected) can be controlled to display. When using the external input, set necessary pins with the LCD control register 2 and apply the proper voltage to the pins . The LCD power input pins (VLC3-VLC1) are also used as pins SEG0-SEG2. When SEG0 is selected, the internal power (VDD) is used for the LCD power. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. * 1/2 duty, 1/2 bias * 1/3 duty, 1/3 bias * 1/4 duty, 1/3 bias Table 18 Table 11 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 Maximum number of displayed pixels 64 pixels 96 pixels 128 pixels Used COM pins COM0, COM1 (Note) COM0-COM2 (Note) COM0-COM3 Note. Leave unused COM pins open. SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 P00/SEG16 P03/SEG19 P10/SEG20 P13/SEG23 P20/SEG24 P23/SEG27 P30/SEG28 to to to to to VDD L23 r r r r r r L23 L13 L22 L13 C20 to C23 C30 to C33 .... .... C10 to C13 .... .... .... L21 L13 L23 L22 L21 L20 .... Segment driver Segment driver Segment driver .... Segment driver .... Segment driver L30 to L33 .... Segment driver Common driver Bias control LCD ON/OFF control L12 .... Selector Selector .... Selector .... Selector .... Selector .... Selector Decoder LCD RAM 1/2, 1/3, 1/4 counter LCD clock (from timer LC) L11 L10 Register A Fig 43. LCD controller/driver Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 43 of 146 P33/SEG31 SEG15 COM3 COM2 COM1 COM0 SEG3 4559 Group (2) LCD clock control The LCD clock is determined by the timer LC setting value and timer LC count source. After setting data to timer LC, timer LC starts counting by setting count source with bit 2 of register W4 and setting bit 3 of register W4 to "1." Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers ((1) to (3)) shown below the formula correspond to numbers in Figure 44, respectively. * When using the system clock (STCK) as timer LC count source (W42="1") F = STCK x (1) 1 LC + 1 (2) x 1 2 (3) [LC: 0 to 15] * When using the bit 4 of timer 3 as timer LC count source (W42="0") F = T34 x (1) 1 LC + 1 (2) x 1 2 (3) [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = F n n F (Hz) Frame frequency = (Hz) F: LCD clock frequency 1/n: Duty T34 STCK (1) W42 0 1 W43 (TLCA) (2) Timer LC (4) (3) 1/2 LCD clock Reload register RLC (4) (TLCA) Register A Fig 44. LCD clock control circuit structure (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When "1" is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. Z X Y bit 1 0 1 2 3 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG16 SEG16 SEG16 SEG16 SEG24 SEG24 SEG24 SEG24 SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25 SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26 SEG3 SEG3 SEG3 SEG3 SEG11 SEG11 SEG11 SEG11 SEG19 SEG19 SEG19 SEG19 SEG27 SEG27 SEG27 SEG27 SEG4 SEG4 SEG4 SEG4 SEG12 SEG12 SEG12 SEG12 SEG20 SEG20 SEG20 SEG20 SEG28 SEG28 SEG28 SEG28 SEG5 SEG5 SEG5 SEG5 SEG13 SEG13 SEG13 SEG13 SEG21 SEG21 SEG21 SEG21 SEG29 SEG29 SEG29 SEG29 SEG6 SEG6 SEG6 SEG6 SEG14 SEG14 SEG14 SEG14 SEG22 SEG22 SEG22 SEG22 SEG30 SEG30 SEG30 SEG30 SEG7 SEG7 SEG7 SEG7 SEG15 SEG15 SEG15 SEG15 SEG23 SEG23 SEG23 SEG23 SEG31 SEG31 SEG31 SEG31 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 8 9 10 11 12 13 14 15 COM Fig 45. LCD RAM map Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 44 of 146 4559 Group (4) LCD drive waveform When "1" is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level. 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM. 1 flame M (1, 2, 8) COM0 COM1 1/F COM1 (2/F) Voltage level 0 (bit 0) 1 X X (bit 3) SEG16 COM0 VLC3 VLC1=VLC2 VSS SEG16 COM1 SEG16 COM0 SEG16 VLC3 VLC1=VLC2 VSS ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM. OFF 1 flame (3/F) M (1, 2, 8) COM0 COM1 COM2 1/F COM2 Voltage level 1 (bit 0) 0 1 X (bit 3) COM1 VLC3 VLC2 VLC1 VSS SEG16 COM0 VLC3 VLC2 VLC1 VSS SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 ON OFF ON 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM. 1 flame M (1, 2, 8) COM0 COM1 COM2 COM3 1/F COM3 (4/F) Voltage level 0 (bit 0) 1 0 1 (bit 3) COM2 VLC3 VLC2 VLC1 VSS SEG16 COM1 COM0 VLC3 VLC2 VLC1 VSS F : LCD clock frequency SEG16 COM3 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) ON OFF ON OFF Fig 46. LCD controller/driver structure Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 45 of 146 4559 Group (5) LCD power supply circuit Select the LCD power supply circuit suitable for the using LCD panel. The LCD power supply circuit is fixed by the followings; * The internal dividing resistor is controlled by bit 0 of register L2. * The internal dividing resistor is selected by bit 3 of register L1. * The bias condition is selected by bits 0 and 1 of register L1. * SEG0/VLC3 pin The selection of SEG0/VLC3 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. * SEG1/VLC2, SEG2/VLC1 pin The selection of SEG1/VLC2 pin function is controlled with the bit 2 of register L2. The selection of SEG2/VLC1 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0 < VLC1 < VLC2 < VLC3 to these pins. Short the VLC2 pin and VLC1 pin at 1/2 bias. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value generated internally is output from the VLC1 pin and VLC2 pin. The VLC2 pin and VLC1 pin have the same electric potential at 1/2 bias. When SEG1 and SEG2 pin functions are selected, use the internal dividing resistor (L20 = "0"). In this time, VLC2 and VLC1 are connected to the generated dividing voltage. * Internal dividing resistor The 4553 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to i0i, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to i0i, the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; * L13 = "0", 1/3 bias used: 2r x 3 = 6r * L13 = "0", 1/2 bias used: 2r x 2 = 4r * L13 = "1", 1/3 bias used: r x 3 = 3r * L13 = "1", 1/2 bias used: r x 2 = 2r External power supply VLC3 SEG0 VLC3 VLC3 VLC2 SEG1 VLC2 SEG1 VLC1 SEG2 VLC1 SEG2 VSS (a) Register L2 = (0000)2 VSS (b) Register L2 = (1000)2 External power supply External power supply VLC3 VLC3 VLC3 VLC3 VLC2 VLC2 VLC2 VLC2 VLC1 VLC1 VLC1 VLC1 VSS (c) Register L2 = (1110)2 (d) Register L2 = (1111)2 VSS Fig 47. LCD power supply circuit example (1/3 bias condition selected) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 46 of 146 4559 Group (6) LCD control register * LCD control register L1 Register L1 controls duty/bias selection, LCD operation, internal dividing resistor selection. Set the contents of this register through register A with the TL1A instruction. The TAL1 instruction can be used to transfer the contents of register L1. * LCD control register L2 Register L2 controls internal dividing resistor operation, selection of pin functions; SEG0/VLC3, SEG1/VLC2, SEG2/VLC1. Set the contents of this register through register A with the TL2A instruction. * LCD control register L3 Register L3 controls selection of pin functions; P20/SEG24 to P23/SEG27. Set the contents of this register through register A with the TL3A instruction. * LCD control register C1 Register C1 controls selection of pin functions; P00/SEG16 to P03/SEG19. Set the contents of this register through register A with the TC1A instruction. * LCD control register C2 Register C2 controls selection of pin functions; P10/SEG20 to P13/SEG23. Set the contents of this register through register A with the TC2A instruction. * LCD control register C3 Register C3 controls selection of pin functions; P30/SEG28 to P33/SEG31. The contents of this register through register A with the TC3A instruction. Table 19 LCD control registers (1) LCD control register L1 L13 L12 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1 L11 0 LCD duty and bias selection bits L10 0 1 1 at reset : 00002 2r x 3, 2r x 2 r x 3, r x 2 Stop (OFF) Operating L1 0 1 0 1 1/2 1/3 1/4 at power down : state retained R/W TAL1/TL1A Duty Not available 1/2 1/3 1/3 Bias L11 Not available LCD control register L2 L23 L22 L21 L20 SEG0/VLC3 pin function switch bit (Note 3) SEG1/VLC2 pin function switch bit (Note 4) SEG2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained W TL2A SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid W TL3A LCD control register L3 L33 P23/SEG27 pin function switch bit at reset : 11112 at power down : state retained 0 SEG27 1 P23 0 SEG26 L32 P22/SEG26 pin function switch bit 1 P22 0 SEG25 L31 P21/SEG25 pin function switch bit 1 P21 0 SEG24 L30 P20/SEG24 pin function switch bit 1 P20 Note 1."R" represents read enabled, and "W" represents write enabled. Note 2."r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. Note 3.VLC3 is connected to VDD internally when SEG0 pin is selected. Note 4.Use internal dividing resistor when SEG1 and SEG2 pins are selected. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 47 of 146 4559 Group Table 20 LCD control registers (2) LCD control register C1 C13 P03/SEG19 pin function switch bit C12 P02/SEG18 pin function switch bit C11 P01/SEG17 pin function switch bit C10 P00/SEG16 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG19 P03 SEG18 P02 SEG17 P01 SEG16 P00 at power down : state retained W TC1A LCD control register C2 C23 P13/SEG23 pin function switch bit C22 P12/SEG22 pin function switch bit C21 P11/SEG21 pin function switch bit C20 P10/SEG20 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG23 P13 SEG22 P12 SEG21 P11 SEG20 P00 at power down : state retained W TC2A LCD control register C3 C33 P33/SEG31 pin function switch bit C32 P32/SEG30 pin function switch bit C31 P31/SEG29 pin function switch bit C30 P30/SEG28 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG31 P33 SEG30 P32 SEG29 P31 SEG28 P30 at power down : state retained W TC3A Note 1."R" represents read enabled, and "W" represents write enabled. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 48 of 146 4559 Group RESET FUNCTION System reset is performed by the followings: * "L" level is applied to the RESET pin externally, * System reset instruction (SRST) is executed, * Reset occurs by watchdog timer, * Reset occurs by built-in power-on reset * Reset occurs by voltage drop detection circuit Then when "H" level is applied to RESET pin, software starts from address 0 in page 0. (1) RESET pin input System reset is performed certainly by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. (Note 1) RESET pin (Note 2) Pull-up transistor Internal reset signal Voltage drop detection circuit Power-on reset circuit (Note 1) SRST instruction Watchdog reset signal WEF Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. Fig 48. Structure of RESET pin and its peripherals Reset input 1 machine cycle or more = 0.85VDD RESET 0.3VDD (Note 1) f(RING) Program starts (address 0 in page 0) On-chip oscillator (internal oscillator) is counted 1376 times (Note 2). Notes 1: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: It depends on the internal state at reset. Fig 49. RESET pin input waveform and reset release timing Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 49 of 146 4559 Group (2) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and Vss at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, "L" level is output to RESET pin and system reset is performed. 100s or less VDD (Note) Power-on reset circuit output Internal reset signal Power-on Reset Reset state released Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig 50. Power-on reset operation Table 21 Port state at reset Name Function D0-D4 D0-D4 D5/INT D5 XCIN/D6, XCOUT/D7 XCIN, XCOUT P00/SEG16-P03/SEG19 P00-P03 P10/SEG20-P13/SEG23 P10-P13 P20/SEG24-P23/SEG27 P20-P23 P30/SEG28-P33/SEG31 P30-P33 SEG0/VLC3-SEG2/VLC1 SEG0-SEG2 SEG3-SEG15 SEG3-SEG15 COM0-COM3 COM0-COM3 C/CNTR C/CNTR Note 1. Output latch is set to "1." Note 2. The output structure is N-channel open-drain. Note 3. Pull-up transistor is turned OFF. State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) Sub-clock input High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) VLC3 (VDD) level VLC3 (VDD) level VLC3 (VDD) level "L" (VSS) level Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 50 of 146 4559 Group (4) Internal state at reset Figure 51 and 52 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 51 and 52 are undefined, so set the initial value to them. * Program counter (PC) Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) * Power down flag (P) * External 0 interrupt request flag (EXF0) * Interrupt control register V1 * Interrupt control register V2 * Interrupt control register I1 * Timer 1 interrupt request flag (T1F) * Timer 2 interrupt request flag (T2F) * Timer 3 interrupt request flag (T3F) * Watchdog timer flags (WDF1, WDF2) * Watchdog timer enable flag (WEF) * Timer control register PA * Timer control register W1 * Timer control register W2 *Timer control register W3 * Timer control register W4 * Clock control register MR * Clock control register RG * LCD control register L1 * LCD control register L2 * LCD control register L3 * LCD control register C1 * LCD control register C2 * LCD control register C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 (Interrupt disabled) (Interrupt disabled) (Interrupt disabled) (Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer LC stopped) Fig 51. Internal state at reset (1) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 51 of 146 4559 Group * Key-on wakeup control register K0 * Key-on wakeup control register K1 * Key-on wakeup control register K2 * Key-on wakeup control register K3 * Pull-up control register PU0 * Pull-up control register PU1 * Pull-up control register PU2 * Pull-up control register PU3 * Port output structure control register FR0 * Port output structure control register FR1 * Port output structure control register FR2 * Port output structure control register FR3 * High-order bit reference enable flag (UPTF) * Carry flag (CY) * Register A * Register B * Register D * Register E * Register X * Register Y * Register Z * Stack pointer (SP) * Operation source clock * Ceramic resonator circuit * RC oscillation circuit * Quartz-crystal oscillator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 0 0 x x 0 0 x x 0 0 x 0 0 x x 111 On-chip oscillator (oeprating) Oeprating Stop Oeprating "X" represents undefined. Fig 52. Internal state at reset (2) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 52 of 146 4559 Group VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP JUDGMENT) The built-in voltage drop detection circuit is used to set the voltage drop detection circuit flag (VDF) or to perform system reset. EPOF instruction + POF instruction EPOF instruction + POF2 instruction Internal reset signal Key-on wakeup signal Timer 3 underflow signal S R Q SVDE instruction Internal reset signal S R Q VDD - (Note 1) VSKIP + Voltage drop detection circuit flag VDF Skip judgement (SNZVD instruction) VDCE (Note 2) Flag occurrence (Note 1) VDD - VRST /VRST + + Voltage drop detection circuit reset signal Reset occurrence Voltage drop detection circuit Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. Fig 53. Voltage drop detection reset circuit (1) Operating state of voltage drop detection circuit The voltage drop detection circuit becomes valid by inputting "H" to the VDCE pin and it becomes invalid by inputting "L." When not executing the SVDE instruction under "H" level of the VDCE pin, the voltage drop detection circuit become invalid in power down state (RAM back-up, clock operating mode). As for this, the voltage drop detection circuit becomes valid at returning from power down, again. When executing the SVDE instruction under "H" level of the VDCE pin, the voltage drop detection circuit becomes valid in power down state (RAM back-up, clock operating mode). The state of executing SVDE instruction can be cleared by system reset. Table 22 Operating state of voltage drop detection circuit SVDE instruction at CPU operating No execute x "L" Execute x No execute O "H" Execute O Note. "O" indicates valid, "x" indicates invalid. VDCE pin at power down x x x O Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 53 of 146 4559 Group (2) Voltage drop detection circuit flag (VDF) Voltage drop detection circuit flag (VDF) is set to "1" when the supply voltage goes the skip occurrence voltage (VSKIP) or less. Moreover, voltage drop detection circuit flag (VDF) is cleared to "0" when the supply voltage goes the skip occurrence voltage (VSKIP) or more. The state of the voltage drop detection circuit flag (VDF) can be examined with the skip instruction (SNZVD). Even when the skip instruction is executed, the voltage drop detection circuit flag is not cleared to "0". Refer to the electrical characteristics for skip occurrence voltage value. (3) Voltage drop detection circuit reset System reset is performed when the supply voltage goes the reset occurrence voltage (VRST-) or less. When the supply voltage goes reset release voltage (VRST+) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released . Refer to the electrical characteristics for reset occurrence value and reset release voltage value. VDD VSKIP (skip occurrence voltage) VRST+(reset release voltage) VRST-(reset occurrence voltage) Voltage drop detection circuit flag (VDF) Voltage drop detection circuit reset signal (Note 1) Note 1: Microcomputer starts operation after on-chip oscillator clock is counted 1376 times. Fig 54. Voltage drop detection circuit operation waveform VDD Recommended operating condition min.value VRST+ VRSTNo reset Program failure may occur. Normal operation VDD Recommended operating condition min.value VRST+ VRSTReset (4) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up, depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 55); supply voltage does not fall below to VRST-, and its voltage regoes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that. Fig 55. VDD and VRST- Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 54 of 146 4559 Group POWER DOWN FUNCTION The 4559 Group has 2-type power down functions. System enters into each power down state by executing the following instructions. * Clock operating mode ................. EPOF and POF instructions * RAM back-up mode ................... EPOF and POF2 instructions When the EPOF instruction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction. (1) Clock operating mode The following functions and states are retained. * RAM * Reset circuit * XCIN-XCOUT oscillation * LCD display * Timer 3 (2) RAM back-up mode The following functions and states are retained. * RAM * Reset circuit (3) Warm start condition The system returns from the power down state when; * External wakeup signal is input * Timer 3 underflow occurs in the power down mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is "1." (4) Cold start condition The CPU starts executing the software from address 0 in page 0 when; * external "L" level is input to RESET pin, * execute system reset instruction (SRST instruction) * reset by watchdog timer is performed * reset by internal power-on reset, or * reset by the voltage drop detection circuit is performed. In this case, the P flag is "0." (5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition from the clock operating mode can be identified by examining the state of T3F flag. Table 23 Functions and states retained at power down mode Function Power down mode Clock RAM operating back-up x Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) x (Note 2) Contents of RAM O Interrupt control registers V1, V2 x Interrupt control registers I1 O Selected oscillation circuit O Clock control register MR, RG O Timer 1, Timer 2 functions (Note 3) Timer 3 function O Timer LC function O Watchdog timer function x (Note 4) Timer control registers PA, WA x Timer control registers W1, W3, W4 O LCD display function O LCD control registers L1 to L3, C1 to O C3 Voltage drop detection circuit (Note 6) Port level (Note 7) Key-on wakeup control registers K0 to O K2 Pull-up control registers PU0, PU1 O Port output structure control registers O FR0 to FR2 External interrupt request flags (EXF0) x Timer interrupt request flags (T1F, T2F) (Note 3) Timer interrupt request flag (T3F) O Interrupt enable flag (INTE) x Voltage drop detection circuit flag x (VDF) Watchdog timer flags (WDF1, WDF2) x (Note 4) Watchdog timer enable flag (WEF) x (Note 4) O x O O O (Note 3) (Note 3) (Note 3) x (Note 4) x O (Note 5) O (Note 6) (Note 7) O O O x (Note 3) (Note 3) x x x (Note 4) x (Note 4) Note 1. "O" represents that the function can be retained, and "x" represents that the function is initialized. Registers and flags other than the above are undefined at power down mode, and set an initial value after returning. Note 2. The stack pointer (SP) points the level of the stack register and is initialized to "7" at power down mode. Note 3. The state of the timer is undefined. Note 4. Initialize the WDF1 flag with the WRST instruction, and then go into the power down state. Note 5. LCD is turned off. Note 6. When the SVDE instruction is executed, this function is valid at power down. Note 7. In the power down mode, C/CNTR pin outputs "L" level. However, when the CNTR input is selected (W11, W10="11"), C/CNTR pin is in an input enabled state (output = high-impedance). Other ports retain their respective output levels. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 55 of 146 4559 Group (6) Return signal An external wakeup signal or timer 3 interrupt request flag (T3F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM backup mode because the oscillation is stopped. Table 24 shows the return condition for each return source. (7) Control registers * Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K1 Register K1 controls the return condition and the selection of valid waveform/level of port P1. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K2 Register K2 controls the port P3 and INT pin key-on wakeup function and the selection of return condition of INT pin. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. * Key-on wakeup control register K3 Register K3 controls the selection of return condition and valid waveform/level of port P3. Set the contents of this register through register A with the TK3A instruction. In addition, the TAK3 instruction can be used to transfer the contents of register K3 to register A. Table 24 Return source and return condition Return source Ports P00-P03 Ports P10-P13 Ports P20-P23 Ports P30-P33 Return condition Return by an external falling edge ("H" "L"). Remarks For ports P0 and P1, the key-on wakeup function can be selected by two port unit, for port P2, it can be selected by a unit. The key-on wakeup function can be selected by two port unit. Select the return level ("L" level or "H" level) and return condition (return by level or edge) with register K3 according to the external state before going into the power down state. Select the return level ("L" level or "H" level) with register I1 and return condition (return by level or edge) with register K2 according to the external state before going into the power down state. Clear T3F with the SNZT3 instruction before system enters into the power down state. When system enters into the power down state while T3F is "1", system returns from the state immediately because it is recognized as return condition. * Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. * Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A. * Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P2 pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. In addition, the TAPU2 instruction can be used to transfer the contents of register PU2 to register A. * Pull-up control register PU3 Register PU3 controls the ON/OFF of the ports P3 pull-up transistor. Set the contents of this register through register A with the TPU3A instruction. In addition, the TAPU3 instruction can be used to transfer the contents of register PU3 to register A. * External interrupt control register I1 Register I1 controls the input control and the selection of valid waveform/level of INT pin. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. External wakeup signal Return by an external "H" level or "L" level input, or rising edge ("L" "H") or falling edge ("H" "L"). Return by an external "L" level input, Return by an external "H" level or "L" level input, or rising edge ("L" "H") or falling edge ("H" "L"). When the return level is input, the interrupt request flag (EXF0) is not set. Return by timer 3 underflow or by setting T3F to "1". It can be used in the clock operating mode. INT pin Timer 3 interrupt request flag (T3F) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 56 of 146 4559 Group High-speed mode E Clock operating mode EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time c ) EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time d ) CRCK instruction no execution B Operation state Operation source clock: f(XIN) Ceramic resonator CRCK instruction execution EPOF + POF 2 instruction execution D RAM back-up mode Key-on wakeup (Stabilizing time c ) EPOF + POF 2 instruction execution C Operation state Operation source clock: f(XIN) RC oscillation Key-on wakeup (Stabilizing time d ) MR1, MR0 01 MR1, MR0 10 MR1, MR0 01 MR1, MR0 00 Internal mode EPOF + POF instruction execution Reset A Operation state Operation source clock: f(RING) On-chip oscillator MR1, MR0 00 (Stabilizing time a ) Key-on wakeup Timer 3 underflow (Stabilizing time b ) EPOF + POF 2 instruction execution Key-on wakeup (Stabilizing time b ) MR1, MR0 10 Low-speed mode EPOF + POF instruction execution Key-on wakeup Timer 3 underflow (Stabilizing time e ) D Operation state Operation source clock: f(XCIN) Quartz-crystal oscillation EPOF + POF 2 instruction execution Key-on wakeup (Stabilizing time e ) f(RING): stop f(XIN): stop f(XCIN): stop f(RING): stop f(XIN): stop f(XCIN): operating Stabilizing time Stabilizing time Stabilizing time Stabilizing time Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times. b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio X 171) times. c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times. d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times. e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times. Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down. The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG before transition to the power down state. 2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state. 3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state. 4: The state after system is released from reset; * A ceramic resonator is selected as the main clock (f(XIN)). * Main clock (f(XIN)) and Sub-clock (f(XCIN)) are valid. 5: When the RC oscillation circuit is used, executing the CRCK instruction is required. If the CRCK instruction is not executed, the ceramic resonator is selected as the main clock f(XIN). 6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG, and generate the wait time until the oscillation is stabilized, and then, switch the system clock. 7: The Sub-clock (quartz-crystal oscillation) is operating except in state D. Fig 56. State transition POF or EPOF instruction + POF2 instruction Reset input Power down flag P S Q P SNZP instruction Program start Yes Warm start R P = "1" ? No Cold start POF or Set source * * * * * * * EPOF instruction + POF2 instruction Clear source * * * * * * System reset Yes T3F = "1" ? No SNZT3 instruction Return from timer 3 underflow Return from external wakeup signal Fig 57. Set source and clear source of the P flag Fig 58. Start condition identified example using the SNZP instruction Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 57 of 146 4559 Group Table 25 Key-on wakeup control register Key-on wakeup control register K0 K03 K02 K01 K00 Ports P12, P13 key-on wakeup control bit Ports P10, P11 key-on wakeup control bit Ports P02, P03 key-on wakeup control bit Ports P00, P01 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/TK1A Key-on wakeup control register K1 K13 Port P23 key-on wakeup control bit K12 Port P22 key-on wakeup control bit K11 Port P21 key-on wakeup control bit K10 Port P20 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK2/TK2A Key-on wakeup control register K2 K23 K22 Ports P32, P33 key-on wakeup control bit (Note 3) Ports P30, P31 key-on wakeup control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained K21 INT pin return condition selection bit K20 INT pin key-on wakeup control bit Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup invalid Key-on wakeup valid R/W TAK3/TK3A Key-on wakeup control register K3 K33 Ports P32, P33 return condition selection bit (Note 3) at reset : 00002 at power down : state retained 0 Return by level 1 Return by edge 0 Falling waveform/"L" level Ports P32, P33 valid waveform/level K32 selection bit (Note 3) 1 Rising waveform/"H" level 0 Return by level Ports P30, P31 return condition selection bit K31 (Note 2) 1 Return by edge 0 Falling waveform/"L" level Ports P30, P31 valid waveform/level K30 selection bit (Note 2) 1 Rising waveform/"H" level Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. To be invalid (K22 = "0") key-on wakeup of ports P30 and P31, set the registers K30 and K31 to "0." Note 3. To be invalid (K23 = "0") key-on wakeup of ports P32 and P33, set the registers K32 and K33 to "0." Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 58 of 146 4559 Group Table 26 Pull-up control register Pull-up control register PU0 PU03 Port P03 pull-up transistor control bit PU02 Port P02 pull-up transistor control bit PU01 Port P01 pull-up transistor control bit PU00 Port P00 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON R/W TAPU1/TPU1A at power down : state retained R/W TAPU0/TPU0A Pull-up control register PU1 PU13 Port P13 pull-up transistor control bit PU12 Port P12 pull-up transistor control bit PU11 Port P11 pull-up transistor control bit PU10 Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at power down : state retained Pull-up control register PU2 PU23 Port P23 pull-up transistor control bit PU22 Port P22 pull-up transistor control bit PU21 Port P21 pull-up transistor control bit PU20 Port P20 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at power down : state retained R/W TAPU2/TPU2A Pull-up control register PU3 PU33 Port P33 pull-up transistor control bit at reset : 00002 at power down : state retained R/W TAPU3/TPU3A 0 Pull-up transistor OFF 1 Pull-up transistor ON 0 Pull-up transistor OFF PU32 Port P32 pull-up transistor control bit 1 Pull-up transistor ON 0 Pull-up transistor OFF PU31 Port P31 pull-up transistor control bit 1 Pull-up transistor ON 0 Pull-up transistor OFF PU30 Port P30 pull-up transistor control bit 1 Pull-up transistor ON Note 1."R" represents read enabled, and "W" represents write enabled. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 59 of 146 4559 Group Table 27 Interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 at reset : 00002 at power down : state retained R/W TAI1/TI1A INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 0 instruction)/"L" level Interrupt valid waveform for INT pin/ I12 return level selection bit (Note 2) Rising waveform ("H" level of INT pin is recognized with the SNZI0 1 instruction)/"H" level 0 One-sided edge detected I11 INT pin edge detection circuit control bit 1 Both edges detected 0 Timer 1 count start synchronous circuit not selected INT pin timer 1 count start synchronous I10 circuit selection bit 1 Timer 1 count start synchronous circuit selected Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 60 of 146 4559 Group CLOCK CONTROL The clock control circuit consists of the following circuits. * On-chip oscillator (internal oscillator) * Ceramic resonator * RC oscillation circuit * Quartz-crystal oscillation circuit * Multi-plexer (clock selection circuit) * Frequency divider * Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 59 shows the structure of the clock control circuit. The 4559 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the main clock (f(XIN)) of the 4559 Group. The quartz-crystal oscillator can be used for sub-clock (f(XCIN)). Division circuit Divided by 8 MR1, MR0 11 10 01 MR3, MR2 11 10 System clock (STCK) Internal clock generating circuit (divided by 3) Divided by 4 Divided by 2 01 00 On-chip oscillator (internal oscillator) Instruction clock (INSTCK) RG0 XIN XOUT Ceramic resonance Multiplexer RG1 QS R CRCK instruction Internal reset signal RC oscillation XCIN XCOUT QS Quartz-crystal oscillation R QS R RG2 Key-on wakeup signal Timer 3 underflow signal EPOF instruction + POF instruction EPOF instruction + POF2 instruction Fig 59. Clock control circuit structure Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 61 of 146 4559 Group (1) On-chip oscillator operation After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Main clock generating circuit (f(XIN)) When the MCU operates by the ceramic resonator or the RC oscillator as the main clock (f(XIN)). After system is released from reset, the ceramic oscillation is valid for main clock. The ceramic oscillation is invalid and the RC oscillation circuit is valid with the CRCK instruction. The CRCK instruction can be executed only once. Execute the CRCK instruction in the initial setting routine (executing it in address 0 in page 0 is recommended). When the main clock (f(XIN)) is not used, connect XIN pin to VSS and leave XOUT pin open, and do not execute the CRCK instruction (Figure 61). (3) Ceramic resonator When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT (Figure 62). Do not execute the CRCK instruction in program. (4) RC oscillation When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 63). To select RC oscillation as the system clock, select the main clock (f(XIN) as the system clock by bits 0 and 1 of the clock control register MR. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Main clock (f(XIN)) * Ceramic resonator circuit valid * RC oscillation circuit invalid Reset CRCK * Ceramic resonator circuit invalid * RC oscillation circuit valid Fig 60. Switch to ceramic resonance/RC oscillation 4559 XIN XOUT * Do not use the CRCK instruction in program. Fig 61. Handling of XIN and XOUT when operating onchip oscillator 4559 XIN XOUT Rd CIN COUT not execute the in * Do Externally connectCRCK instructionRd program. Note: a damping resistor depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value because constants such as capacitance depend on the resonator. Fig 62. Ceramic resonator external circuit 4559 R C XIN XOUT * Execute the CRCK instruction in program. Fig 63. External RC oscillation circuit Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 62 of 146 4559 Group (5) External clock When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 64). Do not execute the CRCK instruction. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power down mode (POF and POF2 instructions) cannot be used when using the external clock. (6) Sub-clock generating circuit f(XCIN) Sub-clock signal f(XCIN) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit and a quartz-crystal oscillator to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 65). XCIN pin and XCOUT pin are also used as ports D6 and D7, respectively. The sub-clock oscillation circuit is invalid and the function of ports D6 and D7 are valid by setting bit 2 of register RG to "1". When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to VSS and leave XCOUT/D7 open. 4559 not use * Doprogram. the CRCK instruction in XOUT VDD VSS XIN External oscillation circuit Fig 64. External clock input circuit 4559 XCIN XCOUT Rd CIN COUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manufacturer's recommended value because constants such as capacitance depend on the resonator. Fig 65. External quarts-crystal circuit Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 63 of 146 4559 Group (7) Clock control register MR Register MR controls system clock and operation mode (frequency division of system clock). Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 28 Clock control registers Clock control register MR MR3 Operation mode selection bits MR2 at reset : 11002 at power down : state retained R/W TAMR/TMRA (8) Clock control register RG Register RG controls the start/stop of each oscillation circuit. Set the contents of this register through register A with the TRGA instruction. MR1 System clock selection bits (Note 2) MR0 MR3 MR2 Operation mode 0 0 Through mode 0 1 Frequency divided by 2 mode 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode System clock MR1 MR0 0 0 f(RING) 0 1 1 1 0 f(XIN) f(XCIN) Not available (Note 3) 1 W TRGA 0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected RG2 Sub-clock (f(XCIN)) control bit (Note 4) 1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected 0 Main clock (f(XIN)) oscillation available RG1 Main-clock (f(XIN)) control bit (Note 4) 1 Main clock (f(XIN)) oscillation stop 0 On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) control bit RG0 (Note 4) 1 On-chip oscillator (f(RING)) oscillation stop Note 1. R" represents read enabled, and "W" represents write enabled. Note 2. The stopped clock cannot be selected for system clock. Note 3. "11" cannot be set to the low-order 2 bits (MR1, MR0) of register MR. Note 4. The oscillation circuit selected for system clock cannot be stopped. Clock control register RG at reset : 0002 at power down : state retained Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 64 of 146 4559 Group QzROM Writing Mode In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is applicable for this microcomputer. Table 29 lists the pin description (QzROM writing mode) and Figure 66 shows the pin connections. Refer to Figure 67 for examples of a connection with a serial programmer. Contact the manufacturer of your serial programmer for serial pro-grammer. Refer to the user 's manual of your serial programmer for details on how to use it. Table 29 Pin description (QzROM writing mode) Pin VDD, VSS RESET XIN, XCIN XOUT, XCOUT D0 - D5 P00/SEG16 - P03/SEG19 P10/SEG20 - P13/SEG23 P20/SEG24 (Note 1) - P23/SEG27 P30/SEG28 - P33/SEG31 CNVSS D4 D3 D2 Name Power source, GND Reset input Clock input Clock output I/O Function Apply 2.7 to 4.7V to VCC, and 0V to VSS. Reset input pin for active "L". Reset occurs when RESET pin is hold at an "L" level for 16 cycles or more of XIN. Either connect an oscillator circuit or connect XIN and XCIN to VSS and leave XOUT and XCOUT open. input input output I/O port I/O Input "H" or "L" level signal or leave the pin open. VPP input SDA input/output SCLK input input I/O input QzROM programmable power source pin. Serial data I/O pin. Serial clock input pin. input Read/program pulse input pin. PGM input Voltage drop VDCE detection circuit input Input "H" or "L" level signal enable Segment output/ SEG0/VLC3 - SEG2/VLC1 LCD power source/ output Either connect to an LCD panel or leave open. SEG3 - SEG15 Common output COM0 - COM3 Output port C/ C/CNTR output C/CNTR pin outputs "L" level. Timer I/O Note 1. Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition period (the period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the P20/SEG24 pin is high inpedance when VPP is approximately 1.3 VDD or grater. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 65 of 146 4559 Group Pin configuration (top view) P10/SEG20 P03/SEG19 P02/SEG18 P01/SEG17 P00/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 29 SEG9 28 39 38 37 36 35 34 33 32 31 30 P11/SEG21 P12/SEG22 P13/SEG23 (Note) P20/SEG24 P21/SEG25 P22/SEG26 P23/SEG27 P30/SEG28 P31/SEG29 P32/SEG30 P33/SEG31 D0 D1 27 SEG8 40 41 42 43 44 45 46 47 48 49 50 51 52 10 11 12 13 1 2 3 4 5 6 7 8 9 26 25 24 23 22 M34559G6FP M34559G6-XXXFP 21 20 19 18 17 16 15 14 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2/VLC1 SEG1/VLC2 SEG0/VLC3 COM3 COM2 COM1 COM0 VDCE XCIN/D6 XCOUT/D7 XOUT D2 D3 D4 XIN CNVss D5/INT RESET Vss VDD C/CNTR VSS PGM SCLK 1K SDA VPP VDD *: Connect an oscillation circuit : QzROM pin OUTLINE PLQP0052JA-A (52P6A-A) Note: Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition period (that period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the P20/SEG24 pin is high impedance when VPP is approximately 1.3 VDD or greater. Fig 66. Pin connection diagram Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 66 of 146 4559 Group 4559 Group T_VDD Vcc T_VPP 4.7 k CNVSS T_TXD T_RXD T_SCLK T_ BUSY T_PGM/OE / MD RESET circuit T_RESET GND 1 k D4 (SDA) D3 (SCLK) N.C. D2 (PGM) RESET Vss XIN XOUT Set the same termination as the single-chip mode. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 67. When using programmer of Suisei Electronics System Co., LTD, connection example Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 67 of 146 4559 Group LIST OF PRECAUTIONS (1) Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. CNVSS is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5k (connect this resistor to CNVSS/VPP pin as close as possible). (2) Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits) (4) Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) (5) Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. (6) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. (7) Multifunction * The input/output of D5 can be used even when INT is used. Be careful when using inputs of both INT and D5 since the input threshold value of INT pin is different from that of port D5. * "H" output function of port C can be used even when the CNTR (output) is used. (8) Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and Vss at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (9) POF, POF2 instruction When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF/POF2 instruction continuously. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 68 of 146 4559 Group (10)D5/INT pin (1) Bit 3 of register I1 When the input of the D5/INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to (1) in Figure 68.) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to (2) in Figure 68.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 68.). (3) Bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to (1) in Figure 70.) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to (2) in Figure 70.). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to (3) in Figure 70.). * * * LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP * * * ; (xxx02) ; The SNZ0 instruction is valid ...... (1) ; (1xxx2) ; Control of INT pin input is changed ...................................................... (2) ; The SNZ0 instruction is executed (EXF0 flag cleared) ...................................................... (3) * * * LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP * * * ; (xxx02) ; The SNZ0 instruction is valid ......(1) ; (x1xx2) ; Interrupt valid waveform is changed .......................................................(2) ; The SNZ0 instruction is executed (EXF0 flag cleared) .......................................................(3) x: these bits are not used here. x: these bits are not used here. Fig 68. External 0 interrupt program example-1 (2) Bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the power down mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the INT pin input is disabled (register I13 = "0"), set the key-on wakeup of INT pin to be invalid (register K20 = "0") before system enters to the power down mode. (refer to (1) in Figure 69.). Fig 70. External 0 interrupt program example-3 * * * LA 0 TK2A DI EPOF POF2 * * * ; (xxx02) ; INT0 key-on wakeup disabled .....(1) ; RAM back-up x: these bits are not used here. Fig 69. External 0 interrupt program example-2 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 69 of 146 4559 Group (11)Prescaler Stop prescaler counting and then execute the TABPS instruction to read its data. Stop prescaler counting and then execute the TPSAB instruction to write data to prescaler. (12)Timer count source Stop timer 1, 2 or LC counting to change its count source. (13)Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. (14)Writing to the timer Stop timer 1, 2 or LC counting and then execute the T1AB, T2AB, T2R2L or TLCA instruction to write data to timer. (15)Writing to reload register In order to write a data to the reload register R1 while the timer 1 is operating, execute the TR1AB instruction except a timing of the timer 1 underflow. In order to write a data to the reload register R2H while the timer 2 is operating, execute the T3HAB instruction except a timing of the timer 2 underflow. (16)PWM signal If the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the PWM signal, a hazard may occur in the PWM output waveform. When "H" interval expansion function of the PWM signal is used, set "1" or more to reload register R2H. Set the port C output latch to "0" to output the PWM signal from C/CNTR pin. (17)Timer 3 Stop timer 3 counting to change its count source. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to "1" till executing the POF instruction. (18)Prescaler, timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) in Figure 71 after prescaler and timer operations start (1) in Figure 71. Time to first underflow (3) in Figure 71 is shorter (for up to 1 period of the count source) than time among next underflow (4) in Figure 71 by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of CNTR input selected by software. (2) Count source Count source (When falling edge of CNTR input is selected) Timer 1 value 3 2 1 0 3 2 1 0 3 2 Timer 1 underflow signal (3) (1) Timer start (4) Fig 71. Timer count start timing and count time when operation starts (1) (19)Timer 2, LC count start timing and count time when operation starts Count starts from the first edge of the count source (2) in Figure 68 after timer 2 and LC operation start (1) in Figure 72. Time to first underflow (3) in Figure 68 is different (for up to 1 period of the count source) from time among next underflow (4) in Figure 72 by the timing to start the timer and count source operations after count starts. (2) Count source Timer value 3 2 1 0 3 2 1 0 3 2 Timer underflow signal (3) (1) Timer start (4) Fig 72. Timer count start timing and count time when operation starts (2) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 70 of 146 4559 Group (20)Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The contents of WDF1 flag and timer WDT are initialized at the power down. * When using the watchdog timer and the power down, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down mode. Also, set the NOP instruction after the WRST instruction, for the case when a skip is performed with the WRST instruction. (21)Voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 73); supply voltage does not fall below to VRST-, and its voltage regoes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that. (23)RC oscillation The CRCK instruction can be executed only once after reset release. Execute the CRCK instruction in the initial setting routine (executing it in address 0 in page 0 is recommended). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. (24)External clock Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power-down mode (POF or POF2 instruction) cannot be used when using the external clock. (25)QzROM (1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritten because of overvoltage. Take care especially at turning on the power. (2) As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx. 0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. (26)Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted. (27)Data Required for QzROM Writing Orders The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. VDD Recommended operating condition min. value VRST+ VRSTNo reset Program failure may occur. Normal operation VDD Recommended operating condition min. value VRST+ VRSTReset Fig 73. VDD and VRST(22)On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 71 of 146 4559 Group NOTES ON NOISE Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. (1) Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring. * Reason In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT VSS XIN XOUT VSS N.G. Fig 75. Wiring for clock I/O pins O.K. * Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring to CNVSS pin Connect an approximately 5 k resistor to the VPP pin and also to the GND pattern supplied to the VSS pin with shortest possible wiring. * Reason The CNVSS pin is the power source input pin for the built-in QzROM. When programming in the built-in QzROM, the impedance of the CNVSS pin is low to allow the electric current for writing flow into the QzROM. Because of this, noise can enter easily. If noise enters the CNVSS pin, abnormal instruction codes or data are read from the built-in QzROM, which may cause a program runaway. Noise Reset circuit VSS RESET VSS N.G. Reset circuit VSS RESET VSS (Note) T he shortest O.K. Fig 74. Wiring for the RESET input pin (2) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. C N V ss about 5k VSS (Note) T he shortest N ote: T his indicates pin. Fig 76. Wiring for CNVSS pin Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 72 of 146 4559 Group (2) Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VDD line as follows: * Connect a bypass capacitor across the VSS pin and the VDD pin at equal length. * Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VDD line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. * Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. VDD VDD Do not cross CNTR XIN XOUT VSS VSS VSS N.G. O.K. N.G. Fig 79. Wiring to a signal line where potential levels change frequently (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. Fig 77. Bypass capacitor across the VSS line and the VDD line (3) Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. * Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Microcomputer Mutual inductance M Separate the VSS line for oscillation from other VSS lines Large current GND XIN XOUT VSS Fig 80. VSS pattern on the underside of an oscillator Fig 78. Wiring for a large current signal line Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 73 of 146 4559 Group (4) Setup for I/O ports Setup I/O ports using hardware and software as follows: Main routine (SWDT) N Interrupt processing routine (SWDT) (SWDT)-1 Interrupt processing EI Main processing (SWDT) 0? N (SWDT) = N? N Main routine errors 0 >0 RTI Return Interrupt processing routine errors Fig 81. Watchdog timer by software Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 74 of 146 4559 Group CONTROL REGISTERS Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 Not used V10 External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) at reset : 00002 at power down : 00002 R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) at reset : 00002 at power down : state retained R/W TAI1/TI1A Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 0 instruction)/"L" level Interrupt valid waveform for INT pin/ I12 return level selection bit (Note 2) Rising waveform ("H" level of INT pin is recognized with the SNZI0 1 instruction)/"H" level 0 One-sided edge detected I11 INT pin edge detection circuit control bit 1 Both edges detected 0 Timer 1 count start synchronous circuit not selected INT pin timer 1 count start synchronous I10 circuit selection bit 1 Timer 1 count start synchronous circuit selected Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 75 of 146 4559 Group Clock control register MR MR3 Operation mode selection bits MR2 at reset : 11002 at power down : state retained R/W TAMR/TMRA MR1 System clock selection bits (Note 2) MR0 Operation mode MR3 MR2 0 0 Through mode 0 1 Frequency divided by 2 mode 1 0 Frequency divided by 4 mode 1 1 Frequency divided by 8 mode MR1 MR0 System clock 0 0 f(RING) 0 1 1 1 0 f(XIN) f(XCIN) Not available (Note 3) 1 W TRGA 0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected RG2 Sub-clock (f(XCIN)) control bit (Note 4) 1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected 0 Main clock (f(XIN)) oscillation available RG1 Main-clock (f(XIN)) control bit (Note 4) 1 Main clock (f(XIN)) oscillation stop 0 On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) control bit RG0 (Note 4) 1 On-chip oscillator (f(RING)) oscillation stop Note 1. R" represents read enabled, and "W" represents write enabled. Note 2. The stopped clock cannot be selected for system clock. Note 3. "11" cannot be set to the low-order 2 bits (MR1, MR0) of register MR. Note 4. The oscillation circuit selected for system clock cannot be stopped. Clock control register RG at reset : 0002 at power down : state retained Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 76 of 146 4559 Group Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state retained) Operating at power down : 02 W TAPP Timer control register W1 W13 Timer 1 count auto-stop circuit selection bit (Note 2) 0 1 0 1 0 Timer 1 count source selection bits (Note 3) W10 0 1 1 at reset : 00002 at power down : state retained R/W TAW1/TW1A W12 Timer 1 control bit Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input R/W TAW2/TW2A 0 1 0 1 W11 W10 W11 Timer control register W2 W23 CNTR pin function control bit W22 PWM signal "H" interval expansion function control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 W21 Timer 2 control bit W20 Timer 2 count source selection bit CNTR pin output invalid CNTR pin output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 R/W TAW3/TW3A Timer control register W3 W33 Timer 3 count source selection bit W32 Timer 3 control bit 0 1 0 1 0 Timer 3 count value selection bits W30 0 1 1 Timer control register W4 W43 Timer LC control bit W42 Timer LC count source selection bit W41 CNTR pin output auto-control circuit selection bit 0 1 0 1 0 1 0 1 at reset : 00002 XIN input Prescaler output (ORCLK) Stop (initial state) Operating at power down : state retained W31 W30 Count source Underflow every 8192 count Underflow every 16384 count Underflow every 32768 count Underflow every 65536 count at power down : state retained R/W TAW4/TW4A W31 0 1 0 1 at reset : 00002 W40 CNTR pin input count edge selection bit Stop (state retained) Operating Bit 4 (T34) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I10 ="1"). Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 77 of 146 4559 Group LCD control register L1 L13 L12 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit at reset : 00002 0 1 0 1 L11 0 0 1 1 2r x 3, 2r x 2 r x 3, r x 2 Stop (OFF) Operating L1 0 1 0 1 Not available 1/2 1/3 1/4 at power down : state retained R/W TAL1/TL1A Duty Not available 1/2 1/3 1/3 Bias L11 LCD duty and bias selection bits L10 LCD control register L2 L23 L22 L21 L20 SEG0/VLC3 pin function switch bit (Note 3) SEG1/VLC2 pin function switch bit (Note 4) SEG2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained W TL2A SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid LCD control register L3 L33 P23/SEG27 pin function switch bit at reset : 11112 at power down : state retained W TL3A 0 SEG27 1 P23 0 SEG26 L32 P22/SEG26 pin function switch bit 1 P22 0 SEG25 L31 P21/SEG25 pin function switch bit 1 P21 0 SEG24 L30 P20/SEG24 pin function switch bit 1 P20 Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. Note 3. VLC3 is connected to VDD internally when SEG0 pin is selected. Note 4. Use internal dividing resistor when SEG1 and SEG2 pins are selected. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 78 of 146 4559 Group LCD control register C1 C13 C12 C11 C10 P03/SEG19 pin function switch bit P02/SEG18 pin function switch bit P01/SEG17 pin function switch bit P00/SEG16 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG19 P03 SEG18 P02 SEG17 P01 SEG16 P00 at power down : state retained W TC1A LCD control register C2 C23 C22 C21 C20 P13/SEG23 pin function switch bit P12/SEG22 pin function switch bit P11/SEG21 pin function switch bit P10/SEG20 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG23 P13 SEG22 P12 SEG21 P11 SEG20 P10 at power down : state retained W TC2A LCD control register C3 C33 P33/SEG31 pin function switch bit at reset : 11112 at power down : state retained W TC3A 0 SEG31 1 P33 0 SEG30 C32 P32/SEG30 pin function switch bit 1 P32 0 SEG29 C31 P31/SEG29 pin function switch bit 1 P31 0 SEG28 C30 P30/SEG28 pin function switch bit 1 P30 Note 1."R" represents read enabled, and "W" represents write enabled. . Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 79 of 146 4559 Group Key-on wakeup control register K0 K03 K02 K01 K00 Ports P12, P13 key-on wakeup control bit Ports P10, P11 key-on wakeup control bit Ports P02, P03 key-on wakeup control bit Ports P00, P01 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAK0/TK0A Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/TK1A Key-on wakeup control register K1 K13 K12 K11 K10 Port P23 key-on wakeup control bit Port P22 key-on wakeup control bit Port P21 key-on wakeup control bit Port P20 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK2/TK2A Key-on wakeup control register K2 K23 K22 Ports P32, P33 key-on wakeup control bit (Note 3) Ports P30, P31 key-on wakeup control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained K21 INT pin return condition selection bit K20 INT pin key-on wakeup control bit Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup invalid Key-on wakeup valid R/W TAK3/TK3A Key-on wakeup control register K3 K33 Ports P32, P33 return condition selection bit (Note 3) at reset : 00002 at power down : state retained 0 Return by level 1 Return by edge 0 Falling waveform/"L" level Ports P32, P33 valid waveform/level K32 selection bit (Note 3) 1 Rising waveform/"H" level 0 Return by level Ports P30, P31 return condition selection bit K31 (Note 2) 1 Return by edge 0 Falling waveform/"L" level Ports P30, P31 valid waveform/level K30 selection bit (Note 2) 1 Rising waveform/"H" level Note 1. "R" represents read enabled, and "W" represents write enabled. Note 2. To be invalid (K22 = "0") key-on wakeup of ports P30 and P31, set the registers K30 and K31 to "0." Note 3. To be invalid (K23 = "0") key-on wakeup of ports P32 and P33, set the registers K32 and K33 to "0." Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 80 of 146 4559 Group Pull-up control register PU0 PU03 Port P03 pull-up transistor control bit PU02 Port P02 pull-up transistor control bit PU01 Port P01 pull-up transistor control bit PU00 Port P00 pull-up transistor control bit at reset : 00002 0 1 0 1 0 1 0 1 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at power down : state retained R/W TAPU0/TPU0A Pull-up control register PU1 PU13 Port P13 pull-up transistor control bit PU12 Port P12 pull-up transistor control bit PU11 Port P11 pull-up transistor control bit PU10 Port P10 pull-up transistor control bit at reset : 00002 0 1 0 1 0 1 0 1 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at power down : state retained R/W TAPU1/TPU1A Pull-up control register PU2 PU23 Port P23 pull-up transistor control bit PU22 Port P22 pull-up transistor control bit PU21 Port P21 pull-up transistor control bit PU20 Port P20 pull-up transistor control bit at reset : 00002 0 1 0 1 0 1 0 1 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at power down : state retained R/W TAPU2/TPU2A Pull-up control register PU3 PU33 Port P33 pull-up transistor control bit at reset : 00002 at power down : state retained R/W TAPU3/TPU3A 0 Pull-up transistor OFF 1 Pull-up transistor ON 0 Pull-up transistor OFF PU32 Port P32 pull-up transistor control bit 1 Pull-up transistor ON 0 Pull-up transistor OFF PU31 Port P31 pull-up transistor control bit 1 Pull-up transistor ON 0 Pull-up transistor OFF PU30 Port P30 pull-up transistor control bit 1 Pull-up transistor ON Note 1. "R" represents read enabled, and "W" represents write enabled. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 81 of 146 4559 Group Port output structure control register FR0 FR03 Ports P12, P13 output structure selection bit FR02 Ports P10, P11 output structure selection bit FR01 Ports P02, P03 output structure selection bit FR00 Ports P00, P01 output structure selection bit at reset : 00002 0 1 0 1 0 1 0 1 at power down : state retained W TFR0A N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR1A Port output structure control register FR1 FR13 Ports D3 output structure selection bit FR12 Ports D2 output structure selection bit FR11 Ports D1 output structure selection bit FR10 Ports D0 output structure selection bit at reset : 00002 0 1 0 1 0 1 0 1 at power down : state retained N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR2A Port output structure control register FR2 FR23 Ports P32, P33 output structure selection bit FR22 Ports P30, P31 output structure selection bit FR21 Ports D5 output structure selection bit FR20 Ports D4 output structure selection bit at reset : 00002 0 1 0 1 0 1 0 1 at power down : state retained N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR3A Port output structure control register FR3 FR33 Ports P23 output structure selection bit FR32 Ports P22 output structure selection bit FR31 Ports P21 output structure selection bit FR30 Ports P20 output structure selection bit at reset : 00002 0 1 0 1 0 1 0 1 at power down : state retained N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output Note 1. "W" represents write enabled. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 82 of 146 4559 Group INSTRUCTIONS Each instruction is described as follows; 1. Index list of instruction function 2. Machine instructions (index by alphabet) 3. Machine instructions (index by function) 4. Instruction code table SYMBOL Symbol A B DR E V1 V2 I1 PA W1 W2 W3 W4 MR RG L1 L2 L3 C1 C2 C3 K0 K1 K2 K3 PU0 PU1 PU2 PU3 FR0 FR1 FR2 FR3 X Y Z DP PC PCH PCL SK SP CY UPTF RPS R1 R2L Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Clock control register MR (4 bits) Clock control register RG (3 bits) LCD control register L1 (4 bits) LCD control register L2 (4 bits) LCD control register L3 (4 bits) LCD control register C1 (4 bits) LCD control register C2 (4 bits) LCD control register C3 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Key-on wakeup control register K3 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Pull-up control register PU2 (4 bits) Pull-up control register PU3 (4 bits) Port output structure control register FR0 (4 bits) Port output structure control register FR1 (4 bits) Port output structure control register FR2 (4 bits) Port output structure control register FR3 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits x 8) Stack pointer (3 bits) Carry flag High-order bit reference enable flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Symbol R2H RLC PS T1 T2 TLC T1F T2F T3F WDF1 WEF INTE EXF0 VDF P D P0 P1 P2 P3 C INT x y z p n i j A3 A2 A1 A0 () - M (DP) a p, a The symbols shown below are used in the following list of instruction function and the machine instructions. Contents Timer 2 reload register (8 bits) Timer LC reload register (4 bits) Prescaler Timer 1 Timer 2 Timer LC Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Voltage drop detection circuit flag Power down flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Port P3 (4 bits) Port C (1 bit) INT pin (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Decision of state shown before "?" Data exchange between a register and memory C+x ? Note 1. The 4559 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 83 of 146 4559 Group INDEX LIST OF INSTRUCTION FUNCTION Grouping Mnemonic Function (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x, x = 0 to 15 (Y) y, y = 0 to 15 (Z) z, z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 Page 103 122 110 122 110 122 119 122 112 122 104 122 111 122 105 122 110 122 110 122 108 122 Grouping Mnemonic Function (A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (UPTF) = 1, (DR2) 0 (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) + (CY) (CY) Carry (A) (A) + n n = 0 to 15 (A) (A)AND(M(DP)) (A) (A)OR(M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 Page 92 124 104 124 TAB TBA TAY TYA Register to register transfer LA n TABP p TEAB TABE TDA TAD TAZ TAX TASP LXY x, y Arithmetic operation AM AMC An AND OR 87 124 87 124 87 124 87 124 94 124 98 124 96 124 102 124 89 124 95 124 93 122 93 122 92 122 90 122 106 122 SC RC SZC CMA RAR RAM addresses LZ z INY DEY TAM j SB j Bit operation XAM j RAM to register transfer 120 122 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PCL) a6-a0 (PCH) p (PCL) a6-a0 (PCH) p (PCL) (DR2-DR0, A3-A0) 97 124 95 124 101 124 99 126 98 126 RB j SZB j SEAM SEA n XAMD j 120 122 XAMI j 120 122 Comparison operation TMA j 115 122 Branch operation Ba BL p, a BLA p 88 126 88 126 88 126 p=0 to 47 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 84 of 146 4559 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Grouping Mnemonic Function (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (INTE) 0 (INTE) 1 V10 = 0 : (EXF0) = 1 ? (EXF0) 0 V10 = 1 : SNZ0 = NOP I12 = 0 : (INT) = "L" ? I12 = 1 : (INT) = "H" ? (A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) Page 88 126 Grouping Mnemonic Function (PA) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (R17-R14) (B) (R13-R10) (A) (B) (T27-T24) (A) (T23-T20) (R2L7-R2L4) (B) (T27-T24) (B) (R2L3-R2L0) (A) (T23-T20) (A) (T27-T20) (R2L7-R2L0) (R2H7-R2H4) (B) (R2H3-R2H0) (A) Page 116 128 109 128 118 128 109 128 118 128 109 128 119 128 109 128 119 128 104 130 116 130 BM a TPAA TAW1 Subroutine operation BML p, a 89 126 TW1A TAW2 TW2A BMLA p 89 126 TAW3 TW3A RTI Return operation 97 126 96 126 97 126 Timer operation TAW4 TW4A TABPS TPSAB RT RTS DI EI SNZ0 90 128 91 128 99 128 TAB1 T1AB 103 130 102 130 Interrupt operation SNZI0 TAV1 TV1A TAV2 TV2A TAI1 TI1A 99 128 108 128 118 128 TAB2 108 128 118 128 105 128 113 128 T2R2L T2HAB T2AB TR1AB 117 130 104 130 102 130 103 130 103 130 p=0 to 47 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 85 of 146 4559 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Grouping Mnemonic Function (RLC) (A) (TLC) (A) V12 = 0 : (T1F) = 1 ? (T1F) 0 V12 = 1 : SNZT1=NOP V13 = 0 : (T2F) = 1 ? (T2F) 0 V13 = 1 : SNZT2=NOP V20 = 0 : (T3F) = 1 ? (T3F) 0 V20 = 1 : SNZT3=NOP (A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2) (P2) (A) (A) (P3) (P3) (A) (D) 1 (D(Y)) 0, (Y) = 0 to 7 (D(Y)) 1, (Y) = 0 to 7 (D(Y)) = 0 ?, (Y) = 0 to 5 (C) 0 (C) 1 (FR0) (A) (FR1) (A) (FR2) (A) (FR3) (A) (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A) (A) (PU2) (PU2) (A) (A) (PU3) Page 115 130 100 130 Grouping Mnemonic Function (PU3) (A) (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (A) (K3) (K3) (A) (A) (L1) (L1) (A) (L2) (A) (L3) (A) (C1) (A) (C2) (A) (C3) (A) RC oscillation selected (A) (MR) (MR) (A) (RG2-RG0) (A2-A0) (PC) (PC)+1 Transition to clock operating Transition to RAM back-up POF or POF2 instruction (P) = 1 ? (VDF) = 1? (WDF1) = 1 ? (WDF1) 0 Stop of watchdog timer function enabled System reset (UPTF) 0 (UPTF) 1 At power down mode, voltage drop detection circuit valid Page 117 132 105 134 113 134 105 134 113 134 106 134 114 134 106 134 114 134 106 134 114 134 114 134 115 134 111 134 111 134 111 134 90 134 107 134 115 134 117 134 93 136 95 136 95 136 91 136 99 136 100 136 119 136 90 136 101 136 97 136 101 136 101 136 TLCA SNZT1 Timer operation TPU3A TAK0 Input/Output operation LCD operation Clock operation Other operation TK0A TAK1 TK1A TAK2 TK2A TAK3 TK3A TAL1 TL1A TL2A TL3A TC1A TC2A TC3A CRCK TAMR TMRA TRGA NOP POF POF2 EPOF SNZP SNZT2 100 130 SNZT3 100 130 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A CLD RD Input/Output operation 91 132 93 132 91 132 94 132 92 132 94 132 92 132 94 132 89 132 96 132 98 132 102 132 96 132 98 132 112 132 112 132 112 132 113 132 SD SZD RCP SCP TFR0A TFR1A TFR2A TFR3A TAPU0 TPU0A TAPU1 TPU1A TAPU2 TPU2A TAPU3 SNZVD WRST DWDT SRST RUPT SUPT 107 132 116 132 107 132 116 132 107 132 117 132 108 132 SVDE Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 86 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruction D9 code 00 Operation: D0 Number of words 6 n 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition Overflow = 0 0 1 1 0 n n n n20 (A) (A) + n n = 0 to 15 Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. AM (Add accumulator and Memory) Instruction D9 code 00 Operation: D0 Number of words 0 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 1 020 (A) (A)A{(M(DP)) Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruction D9 code 00 Operation: D0 Number of words 0 B 16 1 Grouping: Number of cycles 1 Flag CY 0/1 Skip condition - 0 0 0 0 1 0 1 120 (A) (A) + (M(DP)) + (CY) (CY) Carry Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. AND (logical AND between accumulator and memory) Instruction D9 code 00 Operation: D0 Number of words 1 8 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 0 020 (A) (A) AND (M(DP)) Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 87 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) B a (Branch to address a) Instruction D9 code 01 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Branch operation Flag CY - Skip condition - 1 a6 a5 a4 a3 a2 a1 a0 2 1 8 a 16 +a (PCL) a6 to a0 Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. BL p,a (Branch Long to address a in page p) Instruction D9 code 00 1 Operation: D0 Number of words 2 Number of cycles 2 Flag CY - Skip condition - 1 1 1 p4 p3 p2 p1 p0 2 0 E p 16 +p a 0 p5 a6 a5 a4 a3 a2 a1 a0 2 2 (PCH) p (PCL) a6 to a0 a 16 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p = 0 to 47 BLA p (Branch Long to address (D)+(A) in page p) Instruction D9 code 00 1 Operation: D0 Number of words 1 p 0 16 2 Number of cycles 2 Flag CY - Skip condition - 0 0 0 1 0 0 0 020 0 p5 p4 0 0 p3 p2 p1 p0 2 2 (PCH) p (PCL) (DR2-R0, A3-A0) p 16 Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p = 0 to 47 BM a (Branch and Mark to address a in page 2) Instruction D9 code 01 Operation: D0 Number of words a a 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 a6 a5 a4 a3 a2 a1 a0 2 1 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 88 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BML p,a (Branch and Mark Long to address a in page p) Instruction D9 code 00 1 Operation: D0 Number of words 2 Number of cycles 2 Flag CY - Skip condition - 1 1 0 p4 p3 p2 p1 p0 2 0 c p 16 +p a 0 p5 a6 a5 a4 a3 a2 a1 a0 2 2 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 a 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p = 0 to 47 Be careful not to over the stack because the maximum level of subroutine nesting is 8. BMLA p (Branch and Mark Long to address (D)+(A) in page p) Instruction D9 code 00 1 Operation: D0 Number of words 3 p 0 16 2 Number of cycles 2 Flag CY - Skip condition - 0 0 1 1 0 0 0 020 0 p5 p4 0 0 p3 p2 p1 p0 2 2 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) p 16 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p = 0 to 47 Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) Instruction D9 code 00 Operation: D0 Number of words 1 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 0 0 120 (D) 1 Input/Output operation Description: Sets (1) to port D. CMA (CoMplement of Accumulator) Instruction D9 code 00 Operation: D0 Number of words 1 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 0 020 (A) (A) Arithmetic operation Description: Stores the one's complement for register A's contents in register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 89 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) CRCK (Clock select: Rc oscillation ClocK) Instruction D9 code 10 Operation: D0 Number of words 9 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 0 1 1 0 1 122 RC oscillation circuit selected Clock control operation Description: Selects the RC oscillation circuit for main clock f(XIN). DEY (DEcrement register Y) Instruction D9 code 00 Operation: D0 Number of words 1 7 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition (Y) = 15 0 0 0 1 0 1 1 120 (Y) (Y) -1 Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. DI (Disable Interrupt) Instruction D9 code 00 Operation: D0 Number of words 0 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 0 1 0 020 (INTE) 0 Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruction D9 code 10 Operation: D0 Number of words 9 C 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 1 0 0 1 1 1 0 022 Stop of watchdog timer function enabled Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 90 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EI (Enable Interrupt) Instruction D9 code 00 Operation: D0 Number of words 0 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 0 1 0 120 (INTE) 1 Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle. EPOF (Enable POF instruction) Instruction D9 code 00 Operation: D0 Number of words 5 B 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 1 120 POF instruction or POF2 instruction valid Description: Makes the immediate after POF instruction or POF2 instruction valid by executing the EPOF instruction. IAP0 (Input Accumulator from port P0) Instruction D9 code 10 Operation: D0 Number of words 6 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 0 022 (A) (P0) Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruction D9 code 10 Operation: D0 Number of words 6 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 0 122 (A) (P1) Input/Output operation Description: Transfers the input of port P1 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 91 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP2 (Input Accumulator from port P2) Instruction D9 code 10 Operation: D0 Number of words 6 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 1 022 (A) (P2) Input/Output operation Description: Transfers the input of port P2 to the register A. IAP3 (Input Accumulator from port P3) Instruction D9 code 10 Operation: D0 Number of words 6 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 1 0 0 0 1 122 (A) (P3) Input/Output operation Description: Transfers the input of port P3 to the register A. INY (INcrement register Y) Instruction D9 code 00 Operation: D0 Number of words 1 3 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition (Y) = 0 0 0 0 1 0 0 1 120 (Y) (Y) + 1 Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruction D9 code 00 Operation: D0 Number of words 7 n 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition Continuous description 0 1 1 1 n n n n20 (A) n n = 0 to 15 Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 92 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) LXY x,y (Load register X and Y with x and y) Instruction D9 D0 code 1 1 x3 x2 x1 x0 y3 y2 y1 y0 2 3 Operation: (X) x x = 0 to 15 (Y) y y = 0 to 15 Number of words x y 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY Skip condition Continuous description Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruction D9 code 00 Operation: D0 Number of words 4 8 +z 16 1 Grouping: Number of cycles 1 RAM addresses Flag CY - Skip condition - 0 1 0 0 1 0 Z1 Z0 2 0 (Z) z z = 0 to 3 Description: Loads the value z in the immediate field to register Z. NOP (No OPeration) Instruction D9 code 00 Operation: D0 Number of words 0 0 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 0 020 (PC) (PC) + 1 Description: No operation; Adds 1 to program counter value, and others remain unchanged. OP0A (Output port P0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 0 022 (P0) (A) Input/Output operation Description: Outputs the contents of register A to port P0. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 93 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP1A (Output port P1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 0 122 (P1) (A) Input/Output operation Description: Outputs the contents of register A to port P1. OP2A (Output port P2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 1 022 (P2) (A) Input/Output operation Description: Outputs the contents of the register A to port P2. OP3A (Output port P3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 0 1 122 (P3) (A) Input/Output operation Description: Outputs the contents of the register A to port P3. OR (logical OR between accumulator and memory) Instruction D9 code 00 Operation: D0 Number of words 1 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 0 120 (A) (A) OR (M(DP)) Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 94 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) POF (Power OFf) Instruction D9 code 00 Operation: D0 Number of words 0 2 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 1 020 Transition to clock operating mode Description: Puts the system in clock operating mode by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed just before this instruction, this instruction is equivalent to the NOP instruction. POF2 (Power OFf2) Instruction D9 code 00 Operation: D0 Number of words 0 8 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 1 0 0 020 Transition to RAM back-up mode Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. RAR (Rotate Accumulator Right) Instruction D9 code 00 Operation: D0 Number of words 1 D 16 1 Grouping: Number of cycles 1 Flag CY 0/1 Skip condition - 0 0 0 1 1 1 0 120 CY A3A2A1A0 Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instruction D9 code 00 Operation: D0 Number of words 4 C 16 +j 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition - 0 1 0 0 1 1 j j20 (Mj(DP)) 0 j = 0 to 3 Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 95 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) Instruction D9 code 00 Operation: D0 Number of words 0 6 16 1 Grouping: Number of cycles 1 Flag CY 0 Skip condition - 0 0 0 0 0 1 1 020 (CY) 0 Arithmetic operation Description: Clears (0) to carry flag CY. RCP (Reset Port C) Instruction D9 code 10 Operation: D0 Number of words 8 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 0 0 1 1 0 022 (C) 0 Input/Output operation Description: Clears (0) to port C. RD (Reset port D specified by register Y) Instruction D9 code 00 Operation: D0 Number of words 1 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 020 (D(Y)) 0 (Y) = 0 to 7 Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: (Y) = 0 to 7. Do not execute this instruction if values except above are set to register Y. RT (ReTurn from subroutine) Instruction D9 code 00 Operation: D0 Number of words 4 4 16 1 Grouping: Number of cycles 2 Return operation Flag CY - Skip condition - 0 1 0 0 0 1 0 020 (PC) (SK(SP)) (SP) (SP) -1 Description: Returns from subroutine to the routine called the subroutine. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 96 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTI (ReTurn from Interrupt) Instruction D9 code 00 Operation: D0 Number of words 4 6 16 1 Grouping: Number of cycles 1 Return operation Flag CY - Skip condition - 0 1 0 0 0 1 1 020 (PC) (SK(SP)) (SP) (SP) - 1 Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) Instruction D9 code 00 Operation: D0 Number of words 4 5 16 1 Grouping: Number of cycles 2 Return operation Flag CY - Skip condition Skip at uncondition 0 1 0 0 0 1 0 120 (PC) (SK(SP)) (SP) (SP) - 1 Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. RUPT (Reset UPT flag) Instruction D9 code 00 Operation: D0 Number of words 5 8 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 0 020 (UPTF) 0 Description: Clears (0) to the high-order bit reference enable flag UPTF. Note: Even when the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is not transferred to register D. SB j (Set Bit) Instruction D9 code 00 Operation: D0 Number of words 5 C 16 +j 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition - 0 1 0 1 1 1 j j20 (Mj(DP)) 1 j = 0 to 3 Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 97 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SC (Set Carry flag) Instruction D9 code 00 Operation: D0 Number of words 0 7 16 1 Grouping: Number of cycles 1 Flag CY 1 Skip condition - 0 0 0 0 0 1 1 120 (CY) 1 Arithmetic operation Description: Sets (1) to carry flag CY. SCP (Set Port C) Instruction D9 code 10 Operation: D0 Number of words 8 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 0 0 1 1 0 122 (C) 1 Input/Output operation Description: Sets (1) to port C. SD (Set port D specified by register Y) Instruction D9 code 00 Operation: D0 Number of words 1 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 120 (D(Y)) 1 (Y) = 0 to 7 Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. Note: (Y) = 0 to 7. Do not execute this instruction if values except above are set to register Y. SEA n (Skip Equal, Accumulator with immediate data n) Instruction D9 code 00 0 Operation: 0 D0 Number of words 2 7 5 16 2 Number of cycles 2 Flag CY - Skip condition (A) = n n = 0 to 15 0 0 0 1 1 1 0 1 0 n 1 n 0 n 120 n20 (A) = n ? n = 0 to 15 n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 98 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEAM (Skip Equal, Accumulator with Memory) Instruction D9 code 00 Operation: D0 Number of words 2 6 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (A) = (M(DP)) 0 0 1 0 0 1 1 020 (A) = (M(DP)) ? Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag) Instruction D9 code 00 Operation: D0 Number of words 3 8 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition V10 = 0 : (EXF0) = 1 0 0 1 1 1 0 0 020 V10 = 0 : (EXF0) = 1 ? (EXF0) 0 V10 = 1 : SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is "1". When the EXF0 flag is "0", executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin) Instruction D9 code 00 Operation: D0 Number of words 3 A 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition I12 = 0 : (INT0) = "L" I12 = 1 : (INT0) = "H" 0 0 1 1 1 0 1 020 I12 = 0 : (INT) = "L" ? I12 = 1 : (INT) = "H" ? (I12 : bit 2 of the interrupt control register I1) Description: When I12 = 0 : Skips the next instruction when the level of INT pin is "L". Executes the next instruction when the level of INT pin is "H". When I12 = 1 : Skips the next instruction when the level of INT pin is "H." Executes the next instruction when the level of INT pin is "L". SNZP (Skip if Non Zero condition of Power down flag) Instruction D9 code 00 Operation: D0 Number of words 0 3 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition (P) = 1 0 0 0 0 0 0 1 120 (P) = 1 ? Description: Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0". Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 99 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V12 = 0 : (T1F) = 1 1 0 0 0 0 0 0 022 V12 = 0 : (T1F) = 1 ? (T1F) 0 V12 = 1 : SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Description: When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is "1". When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V13 = 0 : (T2F) = 1 1 0 0 0 0 0 0 122 V13 = 0 : (T2F) = 1 ? (T2F) 0 V13 = 1 : SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Description: When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is "1". When the T2F flag is "0", executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag) Instruction D9 code 10 Operation: D0 Number of words 8 2 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition V20 = 0 : (T3F) = 1 1 0 0 0 0 0 1 022 V20 = 0 : (T3F) = 1 ? (T3F) 0 V20 = 1 : SNZT3 = NOP Description: When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is "1". When the T3F flag is "0", executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. SNZVD (Skip if Non Zero condition of Voltage Detector flag) Instruction D9 code 10 Operation: D0 Number of words 8 A 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition V23 = 0 : (VDF) = 1 1 0 0 0 1 0 1 022 (VDF) = 1? Description: Skips the next instruction when voltage drop detection circuit flag VDF is "1". Execute instruction when VDF is "0". After skipping, the contents of VDF remains unchanged. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 100 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SRST (System ReSet) Instruction D9 code 00 Operation: D0 Number of words 0 1 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 0 0 0 0 0 0 120 System reset Description: System reset occurs. SUPT (Set UPT flag) Instruction D9 code 00 Operation: D0 Number of words 5 9 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 0 1 0 1 1 0 0 120 (UPTF) 1 Description: Sets (1) to the high-order bit reference enable flag UPTF. When the table reference instruction (TABP p) is executed, the high-order 2 bits of ROM reference data is transferred to the low-order 2 bits of register D. SVDE (Set Voltage Detector Enable flag) Instruction D9 code 10 Operation: D0 Number of words 9 3 16 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition - 1 0 0 1 0 0 1 122 Voltage drop detection circuit valid at powerdown mode. Description: Voltage drop detection circuit is valid at powerdown mode (clock operating mode, RAM back-up mode) Note: This instruction can be used only for H version. SZB j (Skip if Zero, Bit) Instruction D9 code 00 Operation: D0 Number of words 2 j 16 1 Grouping: Number of cycles 1 Bit operation Flag CY - Skip condition (Mj(DP)) = 0 j = 0 to 3 0 0 1 0 0 0 j j20 (Mj(DP)) = 0 ? j = 0 to 3 Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0". Executes the next instruction when the contents of bit j of M(DP) is "1". Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 101 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag ) Instruction D9 code 00 Operation: D0 Number of words 2 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (CY) = 0 0 0 1 0 1 1 1 120 (CY) = 0 ? Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is "0". After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is "1". SZD (Skip if Zero, port D specified by register Y) Instruction D9 code 00 0 Operation: 0 D0 Number of words 2 4 16 2 Number of cycles 2 Flag CY - Skip condition (D(Y)) = 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 020 120 (D(Y)) = 0 ? (Y) = 0 to 5 2 B 16 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is "0". Executes the next instruction when the bit is "1". Note: (Y) = 0 to 5. Do not execute this instruction if values except above are set to register Y. T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 0 0 022 (T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 0 0 122 (T27-T24) (B) (R2L7-R2L4) (B) (T23-T20) (A) (R2L3-R2L0) (A) Description: Transfers the contents of register B to the high-order 4 bits (T27-T24) of timer 2 and the high-order 4 bits (R2L7-R2L4) of timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits (T23-T20) of timer 2 and the low-order 4 bits (R2L3-R2L0) of timer 2 reload register R2. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 102 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T2HAB (Transfer data to register R2H from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 9 4 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 1 0 0 1 0 1 0 022 (R2H7-R2H4) (B) (R2H3-R2H0) (A) Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2H. T2R2L (Transfer data to timer 2 from register R2L) Instruction D9 code 10 Operation: D0 Number of words 9 5 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 1 0 0 1 0 1 0 122 (T27-T20) (R2L7-R2L0) Description: Transfers the contents of reload register R2L to timer 2. TAB (Transfer data to Accumulator from register B) Instruction D9 code 00 Operation: D0 Number of words 1 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 1 020 (A) (B) Register to register transfer Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruction D9 code 10 Operation: D0 Number of words 7 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 0 0 022 (B) (T17-T14) (A) (T13-T10) Description: Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 103 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB2 (Transfer data to Accumulator and register B from timer 2) Instruction D9 code 10 Operation: D0 Number of words 7 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 0 0 122 (B) (T27-T24) (A) (T23-T20) Description: Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A. TABE (Transfer data to Accumulator and register B from register E) Instruction D9 code 00 Operation: D0 Number of words 2 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 1 020 (B) (E7-E4) (A) (E3-E0) Register to register transfer Description: Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruction D9 code 00 Operation: D0 Number of words 1 Number of cycles 3 Flag CY - Skip condition - 1 0 p5 p4 p3 p2 p1 p0 2 0 8 p 16 +p Grouping: (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (UPTF) 1 (DR1, DR0) (ROM(PC))9, 8 (DR2) 0 (PC) (SK(SP)) (SP) (SP) - 1 Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the loworder 2 bits (DR1, DR0) of register D, and "0" is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. Note: p = 0 to 47 When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. TABPS (Transfer data to Accumulator and register B from Pre-Scaler) Instruction D9 code 10 Operation: D0 Number of words 7 5 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 1 1 0 1 0 122 (B) (TPS7-TPS4) (A) (TPS3-TPS0) Description: Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 104 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAD (Transfer data to Accumulator from register D) Instruction D9 code 00 Operation: D0 Number of words 5 1 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 0 120 (A2-A0) (DR2-DR0) (A3) 0 Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. "0" is stored to the bit 3 (A3) of register A. TAI1 (Transfer data to Accumulator from register I1) Instruction D9 code 10 Operation: D0 Number of words 5 3 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 0 1 122 (A) (I1) Description: Transfers the contents of interrupt control register I1 to register A. TAK0 (Transfer data to Accumulator from register K0) Instruction D9 code 10 Operation: D0 Number of words 5 6 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 1 1 022 (A) (K0) Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A. TAK1 (Transfer data to Accumulator from register K1) Instruction D9 code 10 Operation: D0 Number of words 5 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 0 0 122 (A) (K1) Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 105 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK2 (Transfer data to Accumulator from register K2) Instruction D9 code 10 Operation: D0 Number of words 5 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 0 1 022 (A) (K2) Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TAK3 (Transfer data to Accumulator from register K3) Instruction D9 code 10 Operation: D0 Number of words 5 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 0 1 122 (A) (K3) Input/Output operation Description: Transfers the contents of key-on wakeup control register K3 to register A. TAL1 (Transfer data to Accumulator from register L1) Instruction D9 code 10 Operation: D0 Number of words 4 A 16 1 Grouping: Number of cycles 1 LCD operation Flag CY - Skip condition - 0 1 0 0 1 0 1 022 (A) (L1) Description: Transfers the contents of LCD control register L1 to register A. TAM j (Transfer data to Accumulator from Memory) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 1 0 0 j j j j22C (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 106 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruction D9 code 10 Operation: D0 Number of words 5 2 16 1 Grouping: Number of cycles 1 Clock operation Flag CY - Skip condition - 0 1 0 1 0 0 1 022 (A) (MR) Description: Transfers the contents of clock control register MR to register A. TAPU0 (Transfer data to Accumulator from register PU0) Instruction D9 code 10 Operation: D0 Number of words 5 7 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 1 1 122 (A) (PU0) Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A. TAPU1 (Transfer data to Accumulator from register PU1) Instruction D9 code 10 Operation: D0 Number of words 5 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 1 1 022 (A) (PU1) Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. TAPU2 (Transfer data to Accumulator from register PU2) Instruction D9 code 10 Operation: D0 Number of words 5 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 1 1 122 (A) (PU2) Input/Output operation Description: Transfers the contents of pull-up control register PU2 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 107 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAPU3 (Transfer data to Accumulator from register PU3) Instruction D9 code 10 Operation: D0 Number of words 5 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 1 1 0 122 (A) (PU3) Input/Output operation Description: Transfers the contents of pull-up control register PU3 to register A. TASP (Transfer data to Accumulator from Stack Pointer) Instruction D9 code 00 Operation: D0 Number of words 5 0 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 0 020 (A2-A0) (SP2-SP0) (A3) 0 Register to register transfer Description: Transfers the contents of stack pointer (SP) to the loworder 3 bits (A2-A0) of register A. "0" is stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruction D9 code 00 Operation: D0 Number of words 5 4 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 1 0 020 (A) (V1) Description: Transfers the contents of interrupt control register V1 to register A. TAV2 (Transfer data to Accumulator from register V2) Instruction D9 code 00 Operation: D0 Number of words 5 5 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 1 0 1 0 1 0 120 (A) (V2) Description: Transfers the contents of interrupt control register V2 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 108 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW1 (Transfer data to Accumulator from register W1) Instruction D9 code 10 Operation: D0 Number of words 4 B 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 0 1 122 (A) (W1) Description: Transfers the contents of timer control register W1 to register A. TAW2 (Transfer data to Accumulator from register W2) Instruction D9 code 10 Operation: D0 Number of words 4 C 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 0 022 (A) (W2) Description: Transfers the contents of timer control register W2 to register A. TAW3 (Transfer data to Accumulator from register W3) Instruction D9 code 10 Operation: D0 Number of words 4 D 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 0 122 (A) (W3) Description: Transfers the contents of timer control register W3 to register A. TAW4 (Transfer data to Accumulator from register W4) Instruction D9 code 10 Operation: D0 Number of words 4 E 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 1 0 0 1 1 1 022 (A) (W4) Description: Transfers the contents of timer control register W4 to register A. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 109 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAX (Transfer data to Accumulator from register X) Instruction D9 code 00 Operation: D0 Number of words 5 2 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 1 020 (A) (X) Register to register transfer Description: Transfers the contents of register X to register A. TAY (Transfer data to Accumulator from register Y) Instruction D9 code 00 Operation: D0 Number of words 1 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 1 1 120 (A) (Y) Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruction D9 code 00 Operation: D0 Number of words 5 3 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 1 0 1 0 0 1 120 (A1, A0) (Z1, Z0) (A3, A2) 0 Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. "0" is stored to the high-order 2 bits (A3, A2) of register A. TBA (Transfer data to register B from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 0 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 1 020 (B) (A) Register to register transfer Description: Transfers the contents of register A to register B. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 110 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TC1A (Transfer data to register C1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 1 0 1 0 0 0 2 2 A 8 16 (C1) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register C1. TC2A (Transfer data to register C2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 1 0 1 0 0 1 2 2 A 9 16 (C2) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register C2. TC3A (Transfer data to register C3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 6 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 0 1 1 022 (C3) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register C3. TDA (Transfer data to register D from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 2 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 120 (DR2-DR0) (A2-A0) Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 111 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruction D9 code 00 Operation: D0 Number of words 1 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 1 020 (E7-E4) (B) (E3-E0) (A) Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3-E0) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. TFR0A (Transfer data to register FR0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 8 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 022 (FR0) (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR0. TFR1A (Transfer data to register FR1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 0 122 (FR1) (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR1. TFR2A (Transfer data to register FR2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 1 022 (FR2) (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR2. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 112 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR3A (Transfer data to register FR3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 0 1 122 (FR3) (A) Input/Output operation Description: Transfers the contents of register A to port output structure control register FR3. TI1A (Transfer data to register I1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 7 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 0 1 0 1 1 122 (I1) (A) Description: Transfers the contents of register A to interrupt control register I1. TK0A (Transfer data to register K0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 1 0 1 122 (K0) (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K0. TK1A (Transfer data to register K1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 4 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 022 (K1) (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K1. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 113 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK2A (Transfer data to register K2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 5 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 1 0 1 0 122 (K2) (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K2. TK3A (Transfer data to register K3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 0 022 (K3) (A) Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K3. TL1A (Transfer data to register L1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 A 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 1 022 (L1) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register L1. TL2A (Transfer data to register L2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 B 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 1 122 (L2) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register L2. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 114 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TL3A (Transfer data to register L3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 0 022 (L3) (A) LCD control operation Description: Transfers the contents of register A to the LCD control register L3. TLCA (Transfer data to timer LC and register RLC from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 0 122 (LC) (A) (RLC) (A) Timer control operation Description: Transfers the contents of register A to timer LC and reload register RLC. TMA j (Transfer data to Memory from Accumulator) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 0 1 1 j j j j22B (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TMRA (Transfer data to register MR from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 6 16 1 Grouping: Number of cycles 1 Clock operation Flag CY - Skip condition - 0 0 0 1 0 1 1 022 (MR) (A) Description: Transfers the contents of register A to clock control register MR. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 115 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPAA (Transfer data to register PA from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 1 0 1 0 1 0 1 0 2 2 A A 16 (PA0) (A0) Description: Transfers the least significant bit of register A (A0) to timer control register PA. TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 5 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 1 1 0 1 0 122 (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. TPU0A (Transfer data to register PU0 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 D 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 0 122 (PU0) (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 E 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 1 022 (PU1) (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU1. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 116 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPU2A (Transfer data to register PU2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 2 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 0 1 1 1 122 (PU2) (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU2. TPU3A (Transfer data to register PU3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 8 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 0 022 (PU3) (A) Input/Output operation Description: Transfers the contents of register A to pull-up control register PU3. TR1AB (Transfer data to register R1 from Accumulator and register B) Instruction D9 code 10 Operation: D0 Number of words 3 F 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 1 1 1 1 1 122 (R17-R14) (B) (R13-R10) (A) Timer control operation Description: Transfers the contents of register B to the high-order 4 bits (R17-R14) of timer 1 reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of timer 1 reload register R1. TRGA (Transfer data to register RG from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 9 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 0 0 122 (RG2-RG0) (A2-A0) Clock control operation Description: Transfers the contents of register A to register RG. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 117 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV1A (Transfer data to register V1 from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 3 F 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 1 1 1 1 1 120 (V1) (A) Description: Transfers the contents of register A to interrupt control register V1. TV2A (Transfer data to register V2 from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 3 E 16 1 Grouping: Number of cycles 1 Interrupt operation Flag CY - Skip condition - 0 0 1 1 1 1 1 020 (V2) (A) Description: Transfers the contents of register A to interrupt control register V2. TW1A (Transfer data to register W1 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 E 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 0 1 1 1 022 (W1) (A) Description: Transfers the contents of register A to timer control register W1. TW2A (Transfer data to register W2 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 0 F 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 0 1 1 1 122 (W2) (A) Description: Transfers the contents of register A to timer control register W2. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 118 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW3A (Transfer data to register W3 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 0 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 1 0 0 0 022 (W3) (A) Description: Transfers the contents of register A to timer control register W3. TW4A (Transfer data to register W4 from Accumulator) Instruction D9 code 10 Operation: D0 Number of words 1 1 16 1 Grouping: Number of cycles 1 Timer operation Flag CY - Skip condition - 0 0 0 1 0 0 0 122 (W4) (A) Description: Transfers the contents of register A to timer control register W4. TYA (Transfer data to register Y from Accumulator) Instruction D9 code 00 Operation: D0 Number of words 0 C 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 0 0 0 0 1 1 0 020 (Y) (A) Register to register transfer Description: Transfers the contents of register A to register Y. WRST (Watchdog timer ReSeT) Instruction D9 code 10 Operation: D0 Number of words 1 Grouping: Number of cycles 1 Other operation Flag CY - Skip condition (WDF1) = 1 1 0 1 0 0 0 0 0 2 2 A 0 16 (WDF1) = 1 ? (WDF1) 0 Description: Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is "1". When the WDF1 flag is "0", executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 119 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAM j (eXchange Accumulator and Memory data) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition - 1 1 0 1 j j j j22D (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruction D9 code 10 Operation: D0 Number of words F j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (Y) = 15 1 1 1 1 j j j j22 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) -1 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruction D9 code 10 Operation: D0 Number of words j 16 1 Grouping: Number of cycles 1 Flag CY - Skip condition (Y) = 0 1 1 1 0 j j j j22E (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 120 of 146 4559 Group Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 121 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 1 0 0 Hexadecim al notation 0 0 0 0 0 1 0 1 0 1 E E F C A Function TAB TBA TAY TYA Register to register transfer 1 1 1 1 1 1 1 1 1 1 (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x x = 0 to 15 (Y) y y = 0 to 15 TEAB TABE 0 0 0 0 1 0 1 0 1 0 0 2 A 1 1 TDA TAD 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 2 5 9 1 1 1 1 1 TAZ 0 0 0 1 0 1 0 0 1 1 0 5 3 1 1 TAX TASP 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 5 5 2 0 1 1 1 1 LXY x, y 1 1 x3 x2 x1 x0 y3 y2 y1 y0 3 x y 1 1 RAM addresses LZ z 0 0 0 1 0 0 1 0 z1 z0 0 4 8 +z 3 1 1 (Z) z z = 0 to 3 INY 0 0 0 0 0 1 0 0 1 1 0 1 1 1 (Y) (Y) + 1 DEY 0 0 0 0 0 1 0 1 1 1 0 1 7 1 1 (Y) (Y) - 1 TAM j 1 0 1 1 0 0 j j j j 2 C j 1 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 XAM j RAM to register transfer 1 0 1 1 0 1 j j j j 2 D j 1 1 XAMD j 1 0 1 1 1 1 j j j j 2 F j 1 1 XAMI j 1 0 1 1 1 0 j j j j 2 E j 1 1 TMA j 1 0 1 0 1 1 j j j j 2 B j 1 1 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 122 of 146 4559 Group Skip condition Carry flag CY Detailed description - - - - - - - - - - Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E3-E0) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A. Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. "0" is stored to the bit 3 (A3) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. "0" is stored to the high-order 2 bits (A3, A2) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. "0" is stored to the bit 3 (A3) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. - - - - - - - - - - - - Continuous description - - - (Y) = 0 - Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 - - - - - (Y) = 15 - (Y) = 0 - - - Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 123 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 n n n n Hexadecim al notation 0 7 n Function LA n 1 1 (A) n n = 0 to 15 TABP p 0 0 1 0 p5 p4 p3 p2 p1 p0 0 8 +p p 1 3 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note 1) (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (UPTF) = 1 (DR1, DR0) (ROM(PC))9, 8 (DR2) 0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) AM Arithmetic operation 0 0 0 0 0 0 1 0 1 0 0 0 A 1 1 AMC 0 0 0 0 0 0 1 0 1 1 0 0 B 1 1 (A) (A) + (M(DP)) + (CY) (CY) Carry (A) (A) + n n = 0 to 15 An 0 0 0 1 1 0 n n n n 0 6 n 1 1 AND OR SC RC SZC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 2 8 9 7 6 F 1 1 1 1 1 1 1 1 1 1 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? CMA RAR 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 C D 1 1 1 1 (A) (A) CY A3A2A1A0 SB j Bit operation 0 0 0 1 0 1 1 1 j j 0 5 C +j C +j j 1 1 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 RB j 0 0 0 1 0 0 1 1 j j 0 4 1 1 SZB j 0 0 0 0 1 0 0 0 j j 0 2 1 1 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 124 of 146 4559 Group Skip condition Carry flag CY Detailed description Continuous description - Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and "0" is stored to the least significant bit (DR2) of register D. When this instruction is executed, 1 stage of stack register (SK) is used. - - - - Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. - 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Overflow = 0 - Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0". Executes the next instruction when the contents of carry flag CY is "1". The contents of carry flag CY remains unchanged. Stores the one's complement for register A's contents in register A. - - - - - - 1 0 - (CY) = 0 - - - 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). - - Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 - Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0". Executes the next instruction when the contents of bit j of M(DP) is "1". Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 125 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 1 1 0 Hexadecim al notation 0 2 6 Function SEAM Comparison operation 1 1 (A) = (M(DP)) ? SEA n 0 0 0 0 1 0 0 1 0 1 0 2 5 2 2 (A) = n ? n = 0 to 15 0 Ba 0 0 1 0 1 1 1 1 n n n n 0 1 7 8 +a E +p a 1 n a 1 1 (PCL) a6-a0 a6 a5 a4 a3 a2 a1 a0 Branch operation BL p, a 0 0 1 1 1 p4 p3 p2 p1 p0 0 p 2 2 (PCH) p (Note 1) (PCL) a6-a0 1 BLA p 0 0 0 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 0 0 2 0 a 0 2 2 (PCH) p (Note 1) (PCL) (DR2-DR0, A3-A0) 1 BM a 0 0 1 p5 p4 0 0 0 p3 p2 p1 p0 2 1 p a p a 1 1 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note 1) (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note 1) (PCL) (DR2-DR0, A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 a6 a5 a4 a3 a2 a1 a0 Subroutine operation BML p, a 0 0 1 1 0 p4 p3 p2 p1 p0 0 C +p a 3 p 4 p 2 2 1 BMLA p 0 1 RTI 0 0 0 0 0 p5 a6 a5 a4 a3 a2 a1 a0 0 0 1 0 0 1 0 0 0 0 0 0 2 0 2 0 a 0 p 6 1 1 2 2 p5 p4 0 1 p3 p2 p1 p0 0 1 1 0 Return operation RT 0 0 0 1 0 0 0 1 0 0 0 4 4 1 2 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 RTS 0 0 0 1 0 0 0 1 0 1 0 4 5 1 2 Note 1.M34571G4: p=0 to 31, M34571G6: p=0 to 47 and M34571GD: p=0 to 127. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 126 of 146 4559 Group Skip condition Carry flag CY Detailed description (A) = (M(DP)) - Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. (A) = n n = 0 to 15 - - - Branch within a page : Branches to address a in the identical page. - - Branch out of a page : Branches to address a in page p. - - Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. - - Call the subroutine in page 2 : Calls the subroutine at address a in page 2. - - Call the subroutine : Calls the subroutine at address a in page p. - - Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. - - Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. - - Skip at uncondition - Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 127 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 Hexadecim al notation 0 0 0 0 0 3 4 5 8 Function DI EI SNZ0 1 1 1 1 1 1 (INTE) 0 (INTE) 1 V10 = 0 : (EXF0) = 1 ? (EXF0) 0 V10 = 1 : SNZ0 = NOP I12 = 0 : (INT) = "L"? I12 = 1 : (INT) = "H"? Interrupt operation SNZI0 0 0 0 0 1 1 1 0 1 0 0 3 A 1 1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TPAA TAW1 TW1A 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 5 3 5 3 5 1 A 4 0 4 0 4 1 4 1 4 F 5 E 3 7 A B E C F D 0 E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (PA) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A) Timer operation TAW2 TW2A TAW3 TW3A TAW4 TW4A Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 128 of 146 4559 Group Skip condition Carry flag CY Detailed description - - V10 = 0 : (EXF0) = 1 - - - Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is "1". When the EXF0 flag is "0", executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 0 : Skips the next instruction when the level of INT pin is "L". Executes the next instruction when the level of INT0 pin is "H". When I12 = 1 : Skips the next instruction when the level of INT pin is "H". Executes the next instruction when the level of INT0 pin is "L". (I12: bit 2 of interrupt control register I1) (INT) = "L" However, I12 = 0 (INT) = "H" However, I12 = 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of register A (A0) to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 129 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 1 0 1 0 1 Hexadecim al notation 2 7 5 Function TABPS 1 1 (B) (TPS7-TPS4) (A) (TPS3-TPS0) (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (R17-R14) (B) (R13-R10) (A) (B) (T27-T24) (A) (T23-T20) (R2L7-R2L4) (B) (T27-T24) (B) (R2L3-R2L0) (A) (T23-T20) (A) (R2H7-R2H4) (B) (R2H3-R2H0) (A) (T27) (R2L) (RLC) (A) (TLC) (A) V12 = 0 : (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1 : SNZT1=NOP TPSAB 1 0 0 0 1 1 0 1 0 1 2 3 5 1 1 TAB1 1 0 0 1 1 1 0 0 0 0 2 7 0 1 1 T1AB 1 0 0 0 1 1 0 0 0 0 2 3 0 1 1 TR1AB 1 0 0 0 1 1 1 1 1 1 2 3 F 1 1 TAB2 Timer operation 1 0 0 1 1 1 0 0 0 1 2 7 1 1 1 T2AB 1 0 0 0 1 1 0 0 0 1 2 3 1 1 1 T2HAB T2R2L TLCA SNZT1 1 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 0 2 2 2 2 9 9 0 8 4 5 D 0 1 1 1 1 1 1 1 1 SNZT2 1 0 1 0 0 0 0 0 0 1 2 8 1 1 1 V13 = 0 : (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1 : SNZT2=NOP SNZT3 1 0 1 0 0 0 0 0 1 0 2 8 2 1 1 V20 = 0 : (T3F) = 1 ? After skipping, (T3F) 0 V20 = 1 : SNZT3=NOP Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 130 of 146 4559 Group Skip condition Carry flag CY Detailed description - - Transfers the high-order 4 bits of prescaler to register B. Transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS. Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. - - - - Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L. - - - - Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1. Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits (R2L7-R2L4) of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits (R2L3-R2L0) of timer 2 and timer 2 reload register R2L. - - - - - - Transfers the contents of register B to the high-order 4 bits (R2H7-R2H4) of timer 2 and timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits (R2H3-R2H0) of timer 2 and timer 2 reload register R2H. Transfers the contents of timer 2 reload register R2L to timer 2. Transfers the contents of register A to timer LC and reload register RLC. When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is "1". When the T1F flag is "0", executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is "1". When the T2F flag is "0", executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is "1". When the T3F flag is "0", executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2) - - - - - V12 = 0 : (T1F) = 1 V13 = 0 : (T2F) = 1 - V20 = 0 : (T3F) = 1 - Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 131 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 Hexadecim al notation 2 2 2 2 2 2 2 2 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 2 6 2 6 2 6 2 1 1 1 2 2 8 8 2 2 2 2 5 2 5 2 5 2 5 0 0 0 1 1 2 2 3 3 1 4 5 4 B C D 8 9 A B 7 D E E F F D 8 Function IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A CLD RD SD Input/Output operation 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 (A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2) (P2) (A) (A) (P3) (P3) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 5 SZD RCP SCP TFR0A TFR1A TFR2A TFR3A TAPU0 TPU0A TAPU1 TPU1A TAPU2 TPU2A TAPU3 TPU3A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (C) 0 (C) 1 (FR0) (A) (FR1) (A) (FR2) (A) (FR3) (A) (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A) (A) (PU2) (PU2) (A) (A) (PU3) (PU3) (A) Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 132 of 146 4559 Group Skip condition Carry flag CY Detailed description - - - - - - - - - - Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to the register A. - - - - - - - - - - - - - Outputs the contents of the register A to port P2. Transfers the input of port P3 to the register A. Outputs the contents of the register A to port P3. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0". Executes the next instruction when a bit of port D specified by register Y is "1". (D(Y)) = 0 Y = 0 to 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clears (0) to port C. Sets (1) to port C. Transfers the contents of register A to port output structure control register FR0. Transfers the contents of register A to port output structure control register FR1. Transfers the contents of register A to port output structure control register FR2. Transfers the contents of register A to port output structure control register FR3. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of pull-up control register PU2 to register A. Transfers the contents of register A to pull-up control register PU2. Transfers the contents of pull-up control register PU3 to register A. Transfers the contents of register A to pull-up control register PU3. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 133 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAK0 TK0A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 Hexadecim al notation 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 1 5 1 5 1 5 2 4 0 0 0 A A 2 9 5 1 0 6 B 9 4 A 5 B C A A B C 8 9 6 B 2 6 9 Function 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (A) (K3) (K3) (A) (A) (L1) (L1) (A) (L2) (A) (L3) (A) (C1) (A) (C2) (A) (C3) (A) RC oscillator selected (A) (MR) (MR) (A) (RG2-RG0) (A2-A0) Input/Output operation LCD operation Clock operation TAK1 TK1A TAK2 TK2A TAK3 TK3A TAL1 TL1A TL2A TL3A TC1A TC2A TC3A CRCK TAMR TMRA TRGA Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 134 of 146 4559 Group Skip condition Carry flag CY Detailed description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transfers the contents of key-on wakeup control register K3 to register A. Transfers the contents of register A to key-on wakeup control register K3. Transfers the contents of the LCD control register L1 to register A. Transfers the contents of register A to the LCD control register L1. Transfers the contents of register A to the LCD control register L2. Transfers the contents of register A to the LCD control register L3. Transfers the contents of register A to the LCD control register C1. Transfers the contents of register A to the LCD control register C2. Transfers the contents of register A to the LCD control register C3. Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. Transfers the contents of register A to clock control register RG. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 135 of 146 4559 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Number of cycles Para meter Type of instructi ons Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOP POF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Hexadecim al notation 0 0 0 0 0 2 Function 1 1 1 1 (PC) (PC) + 1 Transition to clock operating mode POF2 0 0 0 0 0 0 1 0 0 0 0 0 8 1 1 Transition to RAM back-up mode EPOF SNZP 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 5 0 B 3 1 1 1 1 POF or POF2 instruction valid (P) = 1 ? Other operation WRST 1 0 1 0 1 0 0 0 0 0 2 A 0 1 1 (WDF1) = 1 ? (WDF1) 0 DWDT SRST RUPT SUPT SVDE 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 1 2 0 0 0 2 9 0 5 5 9 C 1 8 9 3 1 1 1 1 1 1 1 1 1 1 Stop of watchdog timer function enabled System reset (UPTF) 0 (UPTF) 1 At power down mode, voltage drop detection circuit valid SNZVD 1 0 1 0 0 0 1 0 1 0 2 8 A 1 1 (VDF) = 1? Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 136 of 146 4559 Group Skip condition Carry flag CY Detailed description - - - - - - - - - No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0". Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is "1". When the WDF1 flag is "0", executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. (P) = 1 (WDF1) = 1 - - - - - - - - - Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. System reset occurs. Clears (0) to the high-order bit reference enable flag UPTF. Sets (1) to the high-order bit reference enable flag UPTF. Skips the next instruction when voltage drop detection circuit flag VDF is "1". Execute instruction when VPF is "0". After skipping, the contents of VDF remains unchanged. (VDF) = 1 - - Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode). Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 137 of 146 4559 Group INSTRUCTION CODE TABLE 010000 011000 D9- to 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 to D4 010111 011111 D3- H e x , notation D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 NOP 01 BLA 02 03 04 - - - - 05 TASP TAD TAX TAZ TAV1 06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 08 09 0A 0B - - - - - - - - - - - - - - - - 0C 0D 0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 10-17 18-F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM TABP TABP TABP 0 16 32 TABP TABP TABP 1 17 33 TABP TABP TABP 2 18 34 TABP TABP TABP 3 19 35 TABP TABP TABP 4 20 36 TABP TABP TABP 5 21 37 TABP TABP TABP 6 22 38 TABP TABP TABP 7 23 39 TABP TABP TABP 8 24 40 TABP TABP TABP 9 25 41 TABP TABP TABP 10 26 42 TABP TABP TABP 11 27 43 TABP TABP TABP 12 28 44 TABP TABP TABP 13 29 45 TABP TABP TABP 14 30 46 TABP TABP TABP 15 31 47 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML SRST CLD POF - - - - - - - - SNZP INY DI EI RC SC RD SD - RT RTS TAV2 RTI - - - DEY - - POF2 AND - SNZ0 - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 RUPT SUPT - OR TDA AM TEAB TABE AMC TYA - - - - - - SNZI 0 - - - EPOF SB 0 SB 1 SB 2 SB 3 CMA RAR TAB TAY TBA - TV2A SZC TV1A The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 BL BML BLA BMLA SEA SZD Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 138 of 146 4559 Group INSTRUCTION CODE TABLE 110000 D9- to 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 D4 111111 D3- D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hex, notation 20 - - - - - - - - TPU3A 21 22 23 24 - - - - - - - - - - 25 - - 26 27 28 SNZT 1 SNZT 2 SNZT 3 - - - - - - - 29 - - - 2A WRST - - - - - - - 2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15 2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15 2D 2E 2F 30-3F 0 1 2 3 4 5 6 7 8 9 A B C D E F TW3A OP0A T1AB TW4A OP1A T2AB - - IAP0 TAB1 IAP1 TAB2 - - - TABPS XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15 OP2A OP3A - - - - - TPSAB TAMR IAP2 TAI1 - - IAP3 - - - - - - - - - - - - SVDE T2HA B T2R2 L - - - - - TK1A TK2A TMRA TC3A TI1A - - - - TFR0A - - - - - - - - - TAK0 TAPU0 - - - - - - - - - - - TC1A TC2A TPAA - - - - - TRGA TL1A TFR1A TAK1 TFR2A TAL1 TAK2 TAW1 TAK3 TAW2 - SNZV D - TL2A TK0A TFR3A TL3A TLCA TW1A TW2A - - - - TK3A CRCK RCP DWDT SCP - - - - - TPU0A TAW3 TAPU3 TAW4 TAPU1 - TAPU2 TPU1A TPU2A TR1AB The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 139 of 146 4559 Group Electrical characteristics Absolute maximum ratings Table 30 Absolute maximum ratings Symbol VDD VI VO VO VO Pd Topr Tstg Supply voltage Input voltage P0, P1, P2, P3, D0-D5, RESET, XIN, XCIN, INT, CNTR Parameter Conditions Output transistors in cut-off state Ta = 25 C Ratings -0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 Unit V V V V V mW C C Output voltage P0, P1, P2, P3, D0-D7, RESET Output voltage C/CNTR, XOUT, XCOUT Output voltage SEG0 to SEG31, COM0 to COM3 Power dissipation Operating temperature range Storage temperature range 300 -20 to 85 -40 to 125 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 140 of 146 4559 Group Recommended operating conditions Table 31 Recommended operating conditions 1 (Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (with a ceramic resonator) f(STCK) 6MHz f(STCK) 4.4MHz f(STCK) 2.2MHz f(STCK) 1.1MHz f(STCK) 4.8MHz f(STCK) 3.2MHz f(STCK) 1.6MHz f(STCK) 0.8MHz f(STCK) 4.4 MHz f(STCK) 50 kHz Conditions Min. 4 2.7 2 1.8 4 2.7 2 1.8 2.7 1.8 Limits Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V VDD Supply voltage (when an external clock is used) V VDD VDD VDD VRAM VSS VLC3 VIH Supply voltage (when RC oscillation is used) Supply voltage (when quartz-crystal oscillation is used) Supply voltage (when on-chip oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) "H" level input voltage V V 1.8 5.5 V (at RAM back-up) 1.6 0 1.8 0.8VDD 0.7VDD 0.85VDD 0.85VDD 0.8VDD 0 0 0 0 0 VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V 5.5 VDD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD 0.15VDD -20 -10 -30 -15 -10 -5 -20 -10 24 12 10 4 15 7 5 2 -40 -40 40 40 P0, P1, P2, P3, D0-D5 XIN, XCIN RESET INT CNTR P0, P1, P2, P3, D0-D5 XIN, XCIN RESET INT CNTR P0, P1, P2, P3, D0-D5 C/CNTR V V V V VIL "L" level input voltage V IOH(peak) "H" level peak output current mA IOH(avg) "H" level average output current P0, P1, P2, P3, D0-D5 (Note 2) C/CNTR mA IOL(peak) "L" level peak output current P0, P1, P2, P3, D0-D7, C/CNTR RESET mA IOL(avg) "L" level average output current P0, P1, P2, P3, D0-D7, C/CNTR (Note 2) RESET mA IOH(avg) IOL(avg) "H" level total average current "L" level total average current P0, C/CNTR P1, P2, P3, D0-D5 P0, C/CNTR P1, P2, P3, D0-D7, RESET mA mA Note 1. At 1/2 bias: VLC1 = VLC2 = (1/2)*VLC3 At 1/3 bias: VLC1 = (1/3)*VLC3, VLC2 = (2/3)*VLC3 Note 2. The average output current is the average value during 100ms. Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 141 of 146 4559 Group Table 32 Recommended operating conditions 2 (Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) f(STCK) = f(XIN) Conditions VDD = 4.0 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 4 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2 V to 5.5 V VDD = 1.8 V to 5.5 V Min. Limits Typ. Max. 6 4.4 2.2 1.1 6 4.4 2.2 6 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.4 50 f(STCK)/6 3/f(STCK) 100 Unit MHz f(STCK) = f(XIN)/2 f(STCK) = f(XIN)/4, f(XIN)/8 f(XIN) Oscillation frequency (with an external clock input) f(STCK) = f(XIN) MHz f(STCK) = f(XIN)/2 f(STCK) = f(XIN)/4, f(XIN)/8 f(XIN) f(XCIN) f(CNTR) tw(CNTR) TPON Oscillation frequency (at RC oscillation) (Note 1) Oscillation frequency (at quarts-crystal oscillation) Timer external input frequency Timer external input period ("H" and "L" pulse width) Power-on reset circuit valid supply voltage rising time (Note 2) VDD = 2.7 to 5.5 V Quartz-crystal oscillator CNTR CNTR VDD = 0 1.8V MHz kHz Hz s s Note 1. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Note 2. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage. with a ceramic resonator f(STCK) [MHz] 6 at external clock oscillation f(STCK) [MHz] 4.8 4.4 3.2 2.2 1.6 1.1 Recommended operating conditions 1.8 2 2.7 4 5.5 VDD [V] 0.8 1.8 2 Recommended operating conditions 2.7 4 5.5 VDD [V] at RC oscillation f(STCK) [MHz] at quartz-crystal oscillation f(STCK) [kHz] 4.4 Recommended operating conditions 50 Recommended operating conditions 1.8 5.5 VDD [V] 2.7 5.5 VDD [V] Fig 82. System clock (STCK) operating condition map Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 142 of 146 4559 Group Electrical characteristics Table 33 Electrical characteristics 1 (Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VOH Parameter "H" level output voltage P0, P1, P2, P3, D0-D5 VDD = 5V VDD = 3V VOH "H" level output voltage C/CNTR VDD = 5V VDD = 3V VOL "L" level output voltage P0, P1, P2, P3, D0-D7 C/CNTR VDD = 5V VDD = 3V VOL "L" level output voltage RESET VDD = 5V VDD = 3V VI = VDD Test conditions IOH = -10mA IOH = -3mA IOH = -5mA IOH = -1mA IOH = -20mA IOH = -6mA IOH =-10mA IOH = -3mA IOL = 15mA IOL = 5mA IOL = 9mA IOL = 3mA IOL = 5mA IOL = 1mA IOL = 2mA Min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 Limits Typ. Max. Unit V V IIH "H" level input current IIL "L" level input current RPU VT+ -VT- VT+ -VT- VT+ -VT- f(RING) f(XIN) Pull-up resistor value Hysteresis Hysteresis Hysteresis P0, P1, P2, P3, D0-D5 RESET, XIN, XCIN, INT CNTR P0, P1, P2, P3, D0-D5 RESET, XIN, XCIN, INT CNTR P0, P1, P2, P3 RESET RESET INT CNTR 2 0.9 1.4 0.9 2 0.6 0.9 2 V V A A VI = 0V P0, P1, P2, P3 No pull-up VI = 0V -2 VDD = 5V VDD = 3V 30 50 On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external RC not included) (Note 1) COM output impedance (Note 2) SEG output impedance (Note 2) Internal resistor for LCD power supply VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V 10 %, Ta = center 25 C VDD = 3V 10 %, Ta = center 25 C VDD = 5V VDD = 3V VDD = 5V VDD = 3V When dividing resistor 2r x 3 selected When dividing resistor 2r x 2 selected When dividing resistor r x 3 selected When dividing resistor r x 2 selected 200 100 60 120 1 0.4 0.6 0.3 0.2 0.2 500 250 125 250 k V V V 700 400 17 17 kHz % RCOM RSEG RVLC 300 200 150 100 1.5 2 1.5 2 600 400 300 200 7.5 10 7.5 10 1200 800 600 400 k k k Note 1. When RC oscillation is used, use the external 33 pF capacitor (C). Note 2. The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VLC1 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 143 of 146 4559 Group Table 34 Electrical characteristics 2 (Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol IDD Supply current Parameter at active mode (with a ceramic oscillator) (1, 2) Test conditions VDD = 5V f(XIN) = 6MHz f(RING) = stop f(XCIN) = stop VDD = 5V f(XIN) = 4MHz f(RING) = stop f(XCIN) = stop VDD = 3V f(XIN) = 4MHz f(RING) = stop f(XCIN) = stop f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) VDD = 5V VDD = 3V Min. Limits Typ. Max. 1.2 2.4 1.3 2.6 1.6 3.2 2.2 4.4 0.9 1.8 1 2 1.2 2.4 1.6 3.2 0.3 0.6 0.4 0.5 0.7 7 8 10 14 5 6 7 8 50 60 80 120 10 13 19 31 6 5 0.8 1 1.4 14 16 20 28 10 12 14 16 100 120 160 240 20 26 38 62 12 10 Unit mA mA mA at active mode (with a quartz-crystal oscillator)(1, 2) VDD = 5V f(XIN) = stop f(RING) = stop f(XCIN) = 32 kHz VDD = 3V f(XIN) = stop f(RING) = stop f(XCIN) = 32 kHz A A at active mode (with an on-chip oscillator) (1, 2) VDD = 5V f(XIN) = stop f(RING) = active f(XCIN) = stop VDD = 3V f(XIN) = stop f(RING) = active f(XCIN) = stop A A Ta = 25C 0.1 3 A 10 VDD = 5V 6 VDD = 3V Note 1. The voltage drop detection circuit operation current (IRST) is added. Note 2. When the internal dividing resistors for LCD power are used, the current values according to using resistor values are added. at clock operation mode (POF instruction execution)(1, 2) at RAM back-up mode (POF2 instruction execution)(1) f(XCIN) = 32 kHz A Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 144 of 146 4559 Group Voltage drop detection circuit characteristics Table 35 Voltage drop detection circuit characteristics (Ta = -20 C to 85 C, unless otherwise noted) Symbol VRSTParameter Detection voltage (reset occurs) (Note 1) Ta = 25C -20C Ta < 0C Test conditions Min. 1.6 1.3 1.1 Limits Typ. 1.7 Max. 2.2 2.1 1.8 Unit V VRST+ Detection voltage (reset release) (Note 2) 0C Ta < 50C 50C Ta 85C Ta = 25C -20C Ta < 0C 0C Ta < 50C 50C Ta 85C Ta = 25C -20C Ta < 0C 1.8 1.7 1.4 1.2 2 1.9 1.6 1.4 2.5 2.4 2.1 2.3 2.2 1.9 V VSKIP Detection voltage (skip occurs) (Note 3) V 0C Ta < 50C 50C Ta 85C VRST+ -VRSTIRST Detection voltage hysteresis Operation current (Note 4) TRST Note 1. Note 2. Note 3. Note 4. Note 5. 0.1 V VDD = 5V 30 60 A 15 30 VDD = 3V 6 12 VDD = 1.8V Detection time (Note 5) VDD (VRST- -0.1V) 0.2 1.2 ms The detection voltage (VRST-) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. When the supply voltage goes lower than the detection voltage (VSKIP), the voltage drop detection circuit interrupt request flag (VDF) is set to "1". Voltage drop detection circuit operation current (IRST) is added to IDD (power current) when voltage drop detection circuit is used. The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- -0.1V]. Basic timing diagram Machine cycle Parameter System clock Pin name STCK Mi Mi + 1 Port output D0 to D7 P00 to P03 P10 to P13 P20 to P23 P30 to P33, C D0 to D5 P00 to P03 P10 to P13 P20 to P23 P30 to P33 INT Port input Interrupt input Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 145 of 146 4559 Group PACKAGE OUTLINE JEITA Package Code P-LQFP52-10x10-0.65 RENESAS Code PLQP0052JA-A Previous Code 52P6A-A MASS[Typ.] 0.3g Under development HD *1 39 D 27 40 26 bp b1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 HE E c1 c Reference Symbol Dimension in Millimeters 14 1 ZD Index mark 13 ZE 52 Terminal cross section A2 A c F e y *3 L bp x Detail F L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom 10.0 10.0 1.4 11.8 12.0 11.8 12.0 0.05 0.27 0.09 0 Min 9.9 9.9 Max 10.1 10.1 0.35 12.2 12.2 1.7 0.1 0.15 0.32 0.37 0.30 0.145 0.20 0.125 8 0.65 0.13 0.10 1.1 1.1 0.5 0.65 1.0 Rev.1.04 Aug 23, 2007 REJ03B0188-0104 Page 146 of 146 A1 REVISION HISTORY REVISION HISTORY Rev. 1.00 1.01 1.02 1.03 Date Page Jul 27, 2006 Apr 27, 2007 58 First edition issued 4559 Group Datasheet Description Summary Fig56 stabilizing time b, d: (system clock division ratio x 15) times. (system clock division ratio x 171) times. Fig33 ORCLK Fig34 W30 W33 W33 Timer 3 count source selection bit 1 : Prescaler output (ORCLK)/2 Prescaler output (ORCLK) Timer 1, Timer 2 Explanation of function revised. Segment output "28" "32" Fig. 21 13FF16 17FF16 (7)Interrupt sequence revised. PA0 0 "Stop (state initialized)" "Stop (state retained)" W30, W31 "Timer 3 count source selection bits" "Timer 3 count value selection bits" W30 0 "XIN input" "XCIN input" Table 23: Note 4 is revised. Fig. 56 Note 7 added. (2) Bit 3 of register I1 "(register L10="0")" "(register K20="0")" (3) Bit 2 of register I1 "the external 1 interrupt request flag (EXF0)" "the external 0 interrupt request flag (EXF0)" (27) Data Required for QzROM Writing Orders added. Fig. 76 Note added. Fig. 77 "VCC""VDD" PA0 Prascaler control bit 0 "Stop (state initialized)" "Stop (state retained)" W30, W31 "Timer 3 count source selection bits" "Timer 3 count value selection bits" ORCLK May 25, 2007 All pages "PRELIMINARY" deleted May 30, 2007 32 33 34,74 1/2 1.04 Aug 23, 2007 4 21 25 34 55 57 69 65, 66, 67 QzROM Writing Mode added. 71 72 73 77 84, 85, 86 Index pages added. 109 TAW4 Operation: "(A) (W5)""(A) (W4)" All trademarks and registered trademarks are the property of their respective owners. (1/1) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. 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